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參數資料
| 型號： | TSA5055T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 2.65 GHz bidirectional I2C-bus controlled synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2650 MHz, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SOP-16 |
| 文件頁數： | 5/20頁 |
| 文件大?。?/td> | 101K |
| 代理商： | TSA5055T |
1999 Aug 11
5
Philips Semiconductors
Product specification
2.65 GHz bidirectional I
2
C-bus controlled
synthesizer
TSA5055T
Table 1
Write data format; see notes 1 to 13
Notes
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. T1 = 1: P6 = f
REF
and P7 = f
DIV
.
11. T0 = 1: 3-state charge-pump.
12. OS = 1: Operational amplifier output is switched off (varicap drive disable).
13. X: don’t care.
MA1 and MA0: programmable address bits (see Table 3).
A
:
Acknowledge bit.
N14 to N0: programmable divider bits.
N = N14
×
2
14
+ N13
×
2
13
+ ... + N1
×
2
1
+ N0.
CP: charge-pump current. CP = 0: 50
μ
A; CP = 1: 220
μ
A.
P7 to P4 = 1: open-collector outputs are active.
P7 to P3 and P0 = 0: outputs are in high-impedance state.
P3 and P0 = 1: current-limited outputs are active.
T1, T0 and OS = 0, 0 and 0: normal operation.
BYTE
MSB
DATA BYTE
LSB
COMMAND
Address
Programmable divider
1
0
1
0
0
0
MA1
N10
N2
1
X
MA0
N9
N1
1
X
0
A
A
A
A
A
byte 1
byte 2
byte 3
byte 4
byte 5
N14
N6
CP
P6
N13
N5
T1
P5
N12
N4
T0
P4
N11
N3
1
P3
N8
N0
OS
P0
N7
1
P7
Charge-pump and test bits
Output ports, control bits
READ mode: R/W = 1
; see Table 2
Data can be read out of the TSA5055T by setting the R/W
bit to 1. After the slave address has been recognized, the
TSA5055T generates an Acknowledge signal (A) and the
first data byte (status byte) is transferred to the SDA line
(MSB first). Data is valid on the SDA line while the SCL
clock signal is HIGH.
A second data byte can be read out of the TSA5055T if the
processor generates an Acknowledge signal on the SDA
line. End of transmission will occur if the processor does
not send an Acknowledge signal.
The TSA5055T will then release the data line to allow the
processor to generate a STOP condition. When ports
P3 to P7 are used as inputs, they must be programmed to
their high-impedance state.
The POR flag (Power-On Reset) is set to 1 at power-on
and when V
CC
goes below 3 V. The flag is reset when an
end of data is detected by the TSA5055T (end of a READ
sequence). Control of the loop is made possible with the
in-lock flag FL, which indicates when the loop is
phase-locked (FL = 1).
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