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參數(shù)資料
| 型號： | TSA5060AT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 1.3 GHz I2C-bus controlled low phase noise frequency synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-109-1, SOP-16 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 119K |
| 代理商： | TSA5060AT |
2000 Oct 24
8
Philips Semiconductors
Product specification
1.3 GHz I
2
C-bus controlled low phase
noise frequency synthesizer
TSA5060A
READ mode: R/W = 1
Data can be read out of the TSA5060A by setting bit R/W
to logic 1 (see Table 5). After the slave address has been
recognized, the TSA5060A generates an acknowledge
pulse and the first data byte (status word) is transferred on
the SDA line. Data is valid on the SDA line during a
HIGH-level of the SCL clock signal.
A second data byte can be read out of the TSA5060A if the
microcontroller generates an acknowledge bit on the
SDA line.End oftransmissionwilloccurifnoacknowledge
bit from the controller occurs.The TSA5060A will then
release the data line to allow the microcontroller to
generate a STOP condition. When ports P0 to P2 are
used as inputs, they must be programmed in their
high-impedance state.
The POR flag is set to logic 1 when V
CC
drops below
approximately 2.75 V and at power-on.
It is reset to logic 0 when an end of data is detected by the
TSA5060A (end of a READ sequence).
Control of the loop is made possible with the in-lock flag
which indicates if the loop is phase-locked (bit FL = 1).
The bits I2, I1 and I0 represent the status of the I/O ports
P2, P1 and P0 respectively. A logic 0 indicates a
LOW-level and a logic 1 indicates a HIGH-level.
A built-in 5-level ADC is available at pin ADC. This
converter can be used to feed AFC information to the
microcontroller through the I
2
C-bus. The relationship
between bits A2, A1, A0 and the input voltage at pin ADC
is given in Table 7.
Table 5
Read data format
Note
1.
MSB is transmitted first.
Table 6
Explanation of Table 5
Table 7
ADC levels
Note
1.
Accuracy is
±
0.03 V
CC
.
BYTE
DESCRIPTION
MSB
(1)
LSB
CONTROL
BIT
1
2
address
status byte
1
1
0
I2
0
I1
0
I0
MA1
A2
MA0
A1
1
A
POR
FL
A0
BIT
DESCRIPTION
A
MA1 and MA0
POR
FL
I2, I1 and I0
A2, A1 and A0
acknowledge bit
programmable address bits; see Table 3
Power-on reset flag (bit POR = 1 at power-on)
in-lock flag (bit FL = 1 when the loop is phase-locked)
digital information for I/O ports P2, P1 and P0 respectively
digital outputs of the 5-level ADC; see Table 7
A2
A1
A0
VOLTAGE APPLIED TO PIN ADC
(1)
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0.6V
CC
to V
CC
0.45V
CC
to 0.6V
CC
0.3V
CC
to 0.45V
CC
0.15V
CC
to 0.3V
CC
0 to 0.15V
CC
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TSA5060AT/C1,518 | 功能描述:IC SYNTH FREQ 1.3GHZ 16-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| TSA5060AT/C2,118 | 制造商:NXP Semiconductors 功能描述: |
| TSA5060AT/C2,518 | 制造商:NXP Semiconductors 功能描述: |
| TSA5060ATS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3 GHz I2C-bus controlled low phase noise frequency synthesizer |
| TSA5060ATS/C1,118 | 功能描述:IC SYNTH FREQ 1.3GHZ 16-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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