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參數(shù)資料
| 型號(hào)： | TSA5518M |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 1.3 GHz bidirectional I2C-bus controlled synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, SOT-266-1, SSOP-20 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 161K |
| 代理商： | TSA5518M |
1997 Mar 07
4
Philips Semiconductors
Product specification
1.3 GHz bidirectional I
2
C-bus controlled
synthesizer
TSA5518M
PINNING
SYMBOL
PIN
DESCRIPTION
UD
P7
P5
P4
BS
n.c
RF2
RF1
GND
P1
P0
AS
P6
1
2
3
4
5
6
7
8
9
10
11
12
13
drive output (UD)
P7 output port
P5 output port
P4 output port
bandswitch output for M/O drive
not connected
UHF/VHF signal input 2
UHF/VHF signal input 1
ground
P1 output port (general purpose)
P0 output port (general purpose)
input for Address Selection
P6 port (output/input for general
purpose ADC)
P2 output port (f
DIV
if the test mode
is active)
I
2
C-bus serial data input/output
I
2
C-bus serial clock
voltage supply
not connected
crystal oscillator input
charge-pump output (PD)
P2
14
SDA
SCL
V
CC
n.c
XTAL
PD
15
16
17
18
19
20
Fig.2 Pin configuration.
handbook, halfpage
TSA5518M
MBH947
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
UD
PD
P7
XTAL
P5
n.c.
P4
VCC
BS
RF2
RF1
GND
P1
SCL
n.c.
SDA
P2
P6
AS
P0
FUNCTIONAL DESCRIPTION
The device is controlled via the two wire I
2
C-bus.
For programming, there is one module address (7 bits)
and the R/W bit for selecting READ or WRITE mode.
Write mode
The write data format is summarized in Table 1. After the
address transmission (first byte), data bytes can be sent to
the device. Four data bytes are needed to fully program
the device. The bus transceiver has an auto increment
facility which permits the programming of the device within
one single transmission (address byte + 4 data bytes).
The device can also be partially programmed on the
condition that the first data byte following the address is
byte 2 or 4. The meaning of the bits in the data bytes is
given in Table 3. The first bit of the first data byte
transmitted indicates whether frequency data (first bit = 0)
or charge pump and port information (first bit = 1) will
follow. Until an I
2
C-bus STOP condition is sent by the
controller, additional data bytes can be entered without the
need to re-address the device. This allows a smooth
frequency sweep for fine tuning or AFC purpose. At
power-on the ports are set to the high-impedance state
(open-collector outputs) or at the HIGH level (emitter
follower outputs). The bandswitch output BS provides a
voltage output suitable for the band selection input of
mixer/oscillator ICs TDA5330, TDA5630A and TDA5730.
It is controlled by B1 and B0 bits or P7, P5 and P4 bits
depending on the BSC bit (see Tables 1 to 4). The
7.8125 kHz reference frequency is obtained by dividing
the output of the 4 MHz crystal oscillator by 512. Because
the input of UHF/VHF signal is first divided-by-8 the step
size is 62.5 kHz. A 3.2 MHz crystal can offer step size of
50 kHz.
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