參數(shù)資料
型號(hào): TSA5520
廠商: NXP Semiconductors N.V.
英文描述: 1.3 GHz universal bus-controlled TV synthesizer(1.3 GHz通用總線控制的TV合成器)
中文描述: 1.3 GHz的通用總線控制的電視頻率合成器(1.3千兆赫通用總線控制的電視合成器)
文件頁數(shù): 12/24頁
文件大?。?/td> 285K
代理商: TSA5520
1996 Oct 10
12
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizer
TSA5520; TSA5521
CE input (chip enable/address selection)
V
IL
V
IH
I
IH
I
IL
LOW level input voltage
HIGH level input voltage
HIGH level input current
LOW level input current
0
3
10
1.5
5.5
10
V
V
μ
A
μ
A
V
CE
= 5.5 V
V
CE
= 0 V
SCL and SDA inputs
V
IL
V
IH
I
IH
LOW level input voltage
HIGH level input voltage
HIGH level input current
0
3.0
10
100
1.5
5.5
10
10
10
400
V
V
μ
A
μ
A
μ
A
μ
A
kHz
V
BUS
= 5.5 V; V
CC1
= 0 V
V
BUS
= 5.5 V; V
CC1
= 5.5 V
V
BUS
= 1.5 V; V
CC1
= 0 V
V
BUS
= 0 V; V
CC1
= 5.5 V
I
IL
LOW level input current
f
clk
clock frequency
SDA outputs (I
2
C-bus mode)
I
LO
V
o
output leakage current
output voltage
V
SDA
= 5.5 V
I
sink
= 3 mA
10
0.4
μ
A
V
Charge-pump output CP
|I
ICPH
|
|I
ICPL
|
V
CP
I
LI(off)
HIGH charge-pump current
LOW charge-pump current
output voltage
off-state leakage current
CP = 1
CP = 0
in-lock; T
amb
= 25
°
C
T2 = 0; T1 = 1
15
280
60
1.95
0.5
+15
μ
A
μ
A
V
nA
Tuning voltage output V
tune
I
LO(off)
leakage current when
switched-off
output voltage when the loop is
closed
OS = 1; V
tune
= 33 V
10
μ
A
V
o
OS = 0; T2 = 0; T1 = 0; T0 = 1;
R
L
= 27 k
; V
tune
= 33 V
0.2
32.7
V
3-wire bus timing
(see Figs 6 and 7)
t
HIGH
t
SU;DAT
t
HD;DAT
t
SU;ENSCL
t
HD;ENDAT
t
EN
clock high time
data set-up time
data hold time
enable to clock set-up time
enable to data hold time
enable between two
transmissions
enable to clock active edge hold
time
2
2
2
10
2
10
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
t
HD;ENSCL
6
μ
s
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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