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參數(shù)資料
| 型號： | TSA5522 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 1.4 GHz I2C-bus controlled synthesizer |
| 中文描述： | 1.4千兆赫的I2C總線控制合成器 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 172K |
| 代理商： | TSA5522 |
1996 Jan 23
14
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
Flock flag (FL) definition
When the LOCK output is LOW the maximum frequency
deviation
(
f) from stable frequency can be expressed as
K
K
O
follows:
where:
K
vco
= oscillator slope Hz/V
I
CP
= charge-pump current (A)
K
O
= 4
×
10E6
C1, C2 = loop filter capacitors.
In the application:
K
VCO
= 16 MHz/V (UHF band)
I
CP
= 250
μ
A
C1 = 180 nF, C2 = 39 nF
f =
±
31.2 kHz.
f
--------------
I
CP
C1
C2
C2
+
×
(
)
)
--C1
×
×
±
=
Fig.7 Loop filter.
handbook, halfpage
MBE331
C1
R
C2
Table 9
LOCK output / FL flag setting
DESCRIPTION
CONDITION
MIN.
MAX.
UNIT
μ
s
μ
s
μ
s
μ
s
Time span between actual phase lock and LOCK bit is LOW
(or FL flag = 1)
RSA = 1; RSB = 1
RSA = 1; RSB = 1
RSB = 0
1024
2048
1280
0
1152
2304
1440
300
Time span between the loop losing lock and LOCK bit is
HIGH or (FL flag = 0)
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