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參數(shù)資料
| 型號： | TSA5522M |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 1.4 GHz I2C-bus controlled synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1400 MHz, PDSO20 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 172K |
| 代理商： | TSA5522M |
1996 Jan 23
3
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
QUICK REFERENCE DATA
Note
1.
One band switch buffer ON; I
o
= 20 mA.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CC1
V
CC2
I
CC1
I
CC2
f
RF
V
i(RF)
supply voltage (+5 V)
band switch supply voltage (+12 V)
supply current
band switch supply current
RF input frequency
RF input voltage
4.5
V
CC1
64
25
28
26
20
40
12
22
27
4
20
20
5.5
13.5
30
32
1400
3
3
3
25
25
+85
+150
V
V
mA
mA
MHz
dBm
dBm
dBm
MHz
mA
mA
°
C
°
C
note 1
f
i
= 80 to 150 MHz
f
i
= 150 to 1000 MHz
f
i
= 1000 to 1400 MHz
f
xtal
I
o(PNP)
I
o(NPN)
T
amb
T
stg
crystal oscillator input frequency
PNP band switch buffers output current
NPN open-collector output current
operating ambient temperature
storage temperature (IC)
GENERAL DESCRIPTION
(see Fig.1)
The device is a single chip PLL frequency synthesizer
designed for TV and VCR tuning systems. The circuit
consists of a divide-by-eight prescaler with its own
preamplifier, a 15-bit programmable divider, a crystal
oscillator and its programmable reference divider and a
phase/frequency detector combined with a charge-pump
which drives the tuning amplifier, including 33 V output.
Three high-current PNP band switch buffers are provided
for band switching together with four open-collector NPN
outputs (only one open-collector output on 16-pin
devices). These ports can also be used as input ports [one
Analog-to Digital Converter (ADC) and three general
purpose I/O ports (not available on 16-pin devices)]. An
output is provided to control a Philips mixer/oscillator IC in
combination with the PNP buffers state.
Depending on the reference divider ratio (512, 640
or 1024), the phase comparator operates at 3.90625 kHz,
6.25 kHz or 7.8125 kHz with a 4 MHz crystal. The LOCK
detector bit FL is set to logic 1 when the loop is locked and
is read on the SDA line (status byte) during a read
operation.
The ADC is available for digital AFC control. The ADC
code is read during a read operation on the I
2
C-bus. The
ADC input is combined with the port P6. In the TEST
mode, this port is also used as a TEST output for f
ref
and
1
2
f
div
(see Table 4).
I
2
C-bus format
Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the ports, set the charge-pump current and the reference
divider ratio. The device has three independent I
2
C-bus
addresses selected by applying a specific voltage on AS
input (see Table 3). The general address C2 is always
valid.
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