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參數(shù)資料
| 型號： | TSA5527AM |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 1.3 GHz universal bus-controlled TV synthesizers |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 18/28頁 |
| 文件大?。?/td> | 290K |
| 代理商： | TSA5527AM |
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1996 Sep 24
18
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
Table 16
Two status byte acquisition
Notes
1.
2.
XX = the read status byte.
X = no acknowledge from the master means end of sequence.
Other I
2
C-bus addresses may be selected by applying an appropriate voltage to the CE input.
Examples of 3-wire bus sequences (TSA5526; SW = OPEN)
Table 17
18-bit sequence (f
osc
= 800 MHz, BS4 = ON)
The reference divider is automatically set to 512 unless RSB has been programmed to 0 during a 27-bit sequence
(see Table 19).
Table 18
19-bit sequence (f
osc
= 650 MHz, BS3 = ON)
The reference divider is automatically set to 1024 unless RSB has been programmed to 0 during a 27-bit sequence
(see Table 19).
Table 19
27-bit sequence (f
osc
= 750 MHz, BS1 = ON, N = 640, I
cp
= 60
μ
A, no test function)
Table 20
19-bit sequence
This sequence will program f
osc
to 600 MHz in 50 kHz steps. I
CP
remains at 60
μ
A.
Table 21
18-bit sequence
This sequence will program f
osc
to 600 MHz in 50 kHz steps. I
CP
remains at 60
μ
A.
Table 22
27-bit sequence (f
osc
= 650 MHz, BS1 = ON)
This sequence sets RSA to 0, RSB to 1 and CP to 1. After this sequence I
CP
= 280
μ
A, N = 1024 (19-bit transmission)
and N = 512 (18-bit transmission), RSB = 1.
S
C3
A
XX
(1)
A
XX
(1)
X
(2)
P
1
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
1
1
0
0
1
0
1
0
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