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| 型號： | TSB14AA1I |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 電信提供商/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 26/35頁 |
| 文件大?。?/td> | 224K |
| 代理商： | TSB14AA1I |
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6
–
6
00
11
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
PHY Cti [0:1]
00
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
PHY D [0:7]
00
ZZ
ZZ
ZZ
01
01
10
10
10
10
00
00
ZZ
Link Cti [0:1]
ZZ
ZZ
00
00
D0
D1
D2
Dn
00
00
ZZ
Link D [0:7]
ZZ
Single Packet
ZZ
ZZ
ZZ
ZZ
00
11
00
ZZ
00
ZZ
ZZ
ZZ
PHY Cti [0:1]
ZZ
ZZ
ZZ
00
00
00
ZZ
00
ZZ
ZZ
ZZ
PHY D [0:7]
ZZ
10
10
01
00
ZZ
ZZ
ZZ
01
ZZ
01
10
10
Link Cti [0:1]
Dn-1
00
00
ZZ
ZZ
ZZ
00
ZZ
00
D0
D1
Link D [0:7]
Dn
Continued Packet
ZZ = High- Impedance State
D0 = > Dn = Packet Data
Figure 6
–
4. Transmit Timing
6.1.5
Receive
When data is received by the PHY from the serial bus, it transfers the data to the link for further processing. The PHY
asserts receive (see Table 6
–
1) on the CTL lines and asserts each D terminal high. The PHY indicates the start of
the packet by placing the speed code on the data bus. The PHY then proceeds with the transmission of the packet
to the link on the D lines while keeping the receive status on the CTL terminals. Once the packet has been completely
transferred, the PHY asserts idle on the CTL terminals, which completes the receive operation (see Figure 6
–
5).
NOTE:
The speed code is a PHY-link protocol and is not included in the CRC.
PHY
Ctl[0:1]
PHY
D[0:1]
00
10
10
10
10
10
10
00
00
00
11
11
SPD
D0
D1
Dn
00
00
NOTE A: SPD = Speed Code (for the backplane, this speed is fixed at D0, D1 = 00)
D0 to Dn = Packet data
Figure 6
–
5. Receive Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB14AA1T | FPGA (Field-Programmable Gate Array) |
| TSB14C01MHV | IC APEX 20KE FPGA 160K 484-FBGA |
| TSB14C01HV | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB21LV03MHV | IC APEX 20KE FPGA 200K 484-FBGA |
| TSB21LV03CHV | IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB14AA1PFB | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1PFBG4 | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| TSB14AA1TPFB | 功能描述:IC BACKPLANE PHY 3.3V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| TSB14C01 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
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