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TSC2100
SLAS378 NOVEMBER 2003
www.ti.com
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AUDIO OUTPUT DRIVER POWER-ON POP REDUCTION SCHEME
The TSC2100 implements a pop reduction scheme to reduce audible artifacts during powerup and powerdown of the audio
output drivers. This scheme can be controlled by programming bits D2 and D1 of REG1EH/Page2. By default, the driver
pop reduction scheme is enabled and can be disabled by programming bit D2 of Reg1EH/Page2 to 1. When this scheme
is enabled and the virtual ground connection is not used (VGND amplifier is powered down), the audio output driver slowly
charges up any external ac-coupling capacitors to reduce audible artifacts. Bit D1 of REG1EH/Page2 provides control of
the charging time for the ac-coupling capacitor as either 0.8 sec or 4 sec. When the virtual ground amplifier is powered up
and used, the external ac-coupling capacitor is eliminated, and the powerup time becomes either 1 ms or 5 ms. This scheme
takes effect whenever the audio output drivers are powered up due to enabling any of the DAC, the Analog Mixer or the
Keyclick Generator.
Pop Reduction For DAC Routing
Whenever the audio DAC is powered on or off, there may be a slight change in the output dc offset voltage and can be heard
as a weak pop in the output. In order to reduce this artifact, the TSC2100 implements a DAC pop reduction scheme, which
is programmable using bits D5D2 in REG1DH/Page2. Bit D5 enables the scheme, which implements a slow transition
between the starting dc level and the final dc level. For best results program D4D2 in REG1DH/Page2 to 100.
AUDIO MIXING
Digital Sidetone
The digital sidetone control attenuates the output from the ADCs decimation filter and routes its output to be mixed with
the DAC digital input. If bit D7 of REG03H/Page2 is reset, the output of the sidetone control is mixed with the stereo DAC
input. Care must be taken while selecting the digital sidetone gain such that the output of the digital mixer is not overloaded.
The digital sidetone block implements gains from 0 dB to –48 dB in steps of 1.5 dB. Gain changes are implemented at
zero-crossings of the signal to avoid any audible artifacts. The digital sidetone block is automatically internally disabled
if ADC and DAC are operating at different sampling rates, or if the DAC is powered down.
Analog Mixer
The analog mixer can be used to route the analog input selected for the ADC (MICIN or AUX) through an analog volume
control and then mix it with the audio DAC output. The analog mixer feature is available only if single-ended MICIN or AUX
is selected as the input to the ADC, not when the ADC input is configured in fully-differential mode. This feature is available
even if the ADC and DAC are powered down. The analog volume control in this path has a gain range from 12 dB to
–34.5 dB in 0.5-dB steps plus mute and includes soft-stepping logic. The internal oscillator is used for soft stepping
whenever the ADC and DAC are powered down.
KEYCLICK
A special circuit has been included for inserting a squarewave signal into the analog output signal path based on register
control. This functionality is intended for generating keyclick sounds for user feedback. Register 04H/Page2 contains bits
that control the amplitude, frequency, and duration of the square-wave signal. The frequency of the signal can be varied
from 62.5 Hz to 8 kHz and its duration can be programmed from 2 periods to 32 periods. Whenever this register is written,
the square-wave is generated and coupled into the audio output, going to both audio outputs. The keyclick enable bit D15
of control register 04H/Page2 is reset after the duration of keyclick is played out. This capability is available even when
the ADC and DAC are powered down.
SPI DIGITAL INTERFACE
All TSC2100 control registers are programmed through a standard SPI bus. The SPI allows full-duplex, synchronous, serial
communication between a host processor (the master) and peripheral devices (slaves). The SPI master generates the
synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start and synchronize
transmissions.
A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on the slave SPIDIN
(MOSI) pin under the control of the master serial clock. As the byte shifts in on the SPIDIN pin, a byte shifts out on the
SPIDOUT (MISO) pin to the master shift register.
The idle state of the serial clock for the TSC2100 is low, which corresponds to a clock polarity setting of 0 (typical
microprocessor SPI control bit CPOL = 0). The TSC2100 interface is designed so that with a clock phase bit setting of 1
(typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its
SPIDOUT pin on the first serial clock edge. The SS pin can remain low between transmissions; however, the TSC2100
only interprets command words which are transmitted after the falling edge of SS.