參數(shù)資料
型號: TSC21020F-20MASC
英文描述: IC CYCLONE III FPGA 16K 164 MBGA
中文描述: 數(shù)字信號處理器| 32位|的CMOS | RAD數(shù)據(jù)通信硬|美巡賽| 223PIN |陶瓷
文件頁數(shù): 30/51頁
文件大小: 763K
代理商: TSC21020F-20MASC
30
TSC21020F
4153F
AERO
06/03
AC Parameters
See Figure 15 for voltage reference levels. Use the exact timing information given. Do
not attempt to derive parameters from the addition or subtraction of others. While addi-
tion or subtraction would yield meaningful results for an individual device, the values
given in this data sheet reflect statistical variations and worst cases. Consequently, you
cannot meaningfully add parameters to derive other specifications.
I
DDIDLE
Supply Current (Idle)
8
V
DD
= max, V
IN
= 0V or V
DD
max
150
mA
C
IN
Input Capacitance
9, 10
f
IN
= 1 MHz, T
CASE
= 25
5
C, V
IN
= 2.5V
10
pF
Notes:
1. Applies to: PMD47-0, PMACK, PMTS, DMD39-0, DMACK, DMTS, IRQ3-0, FLAG3-0, BR, TMS, TDI.
2. Applies to: CLKIN, TCK.
3. Applies to: PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR,
DMPAGE, FLAG3-0, TIMEXP, BG.
4. Applies to: PMACK, PMTS, DMACK, DMTS, IRQ3-0, BR, CLKIN, RESET, TCK.
5. Applies to: TMS, TDI, TRST.
6. Applies to: PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR,
DMPAGE, FLAG3-0, TDO.
7. Applies to IVDD pins. At t
CK
= 50ns, I
DDIN
(typical) = 350 mA. See "Power Dissipation" for calculation of external (EVDD)
supply current for total supply current.
8. Applies to IVDD pins. Idle refers to TSC21020F state of operation during execution of the IDLE instruction.
9. Guaranteed but not tested.
10. Applies to all signal pins.
11. Although specified for TTL outputs, all TSC21020F outputs are CMOS-compatible and will drive to V
DD
and GND assuming
no dc loads.
12. Applies to RESET, TRST.
Parameter
Test Conditions
Min
Max
Unit
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