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| 型號(hào)： | TSC21020F-20MASL2 |
| 英文描述： | IC CYCLONE III FPGA 16K 256 UBGA |
| 中文描述： | 數(shù)字信號(hào)處理器| 32位|的CMOS | RAD數(shù)據(jù)通信硬|美巡賽| 223PIN |陶瓷 |
| 文件頁數(shù)： | 40/51頁 |
| 文件大?。?/td> | 763K |
| 代理商： | TSC21020F-20MASL2 |
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40
TSC21020F
4153F
–
AERO
–
06/03
Figure 13.
Output Enable/Disable
Test Conditions
Output Disable Time
Output pins are considered to be disable when they stop driving, go into a high-imped-
ance state, and start to decay from their output high or low voltage. The time for the
voltage on the bus to decay by
V is dependent on the capacitive load, C
L
, and the load
current, I
L
. It can be approximated by the following equation:
The output disable time (t
DIS
) is the difference between t
MEASURED
and t
DECAY
as shown
in Figure 13. The time t
MEASURED
is the interval from when the reference signal switches
to when the output voltage decays
V from the measured output high or output low volt-
age. t
DECAY
is calculated with
V equal to 0.5V, and test loads C
L
and I
L
.
Output Enable Time
Output pins are considered to be enabled when they have made a transition from a
high-impedance state to when they start driving. The output enable time (t
ENA
) is the
interval from when a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown in the Output Enable
/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement
value is that of the first pin to start driving.
t
DECAY
C
V
I
L
--------------
=
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相關(guān)代理商/技術(shù)參數(shù) |
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| TSC21020F-20MASL3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC |
| TSC21020F-20MB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC |
| TSC21020F-20MB/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC |
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| TSC21020F-20MBP833 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC |
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