參數(shù)資料
型號(hào)： TSC2200IRHBR
英文描述： PDA ANALOG INTERFACE CIRCUIT
中文描述： 掌上電腦模擬接口電路
文件頁(yè)數(shù)： 2/40頁(yè)
文件大?。?/td> 645K
代理商： TSC2200IRHBR
2
www.ti.com
TSC2200
SBAS191F
ABSOLUTE MAXIMUM RATINGS
(1)
V
DD
to GND........................................................................
–
0.3V to +6.0V
V
BAT
Input Voltage to GND ...............................................
–
0.3V to +6.0V
Analog Input Voltage to GND (except V
BAT
) ...........
–
0.3V to V
DD
+ 0.3V
Digital Input Voltage to GND ...................................
–
0.3V to V
DD
+ 0.3V
Operating Temperature Range ......................................
–
40
°
C to +105
°
C
Storage Temperature Range .........................................
–
65
°
C to +150
°
C
Junction Temperature (T
J
Max) .................................................... +150
°
C
TSSOP Package
Power Dissipation.................................................... (T
J
Max
–
T
A
)/
θ
JA
θ
JA
Thermal Impedance .......................................................... 90
°
C/W
Lead Temperature, Soldering
Vapor Phase (60s) ............................................................ +215
°
C
Infrared (15s)..................................................................... +220
°
C
NOTE: (1) Stresses above those listed under
“
Absolute Maximum Ratings
”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
INTEGRAL
LINEARITY
ERROR (LSB) PACKAGE-LEAD
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
(1)
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
TSC2200
"
TSC2200
"
±
2
"
±
2
"
TSSOP-28
"
QFN-32
"
PW
"
RHB
"
–
40
°
C to +85
°
C
"
–
40
°
C to +85
°
C
"
TSC2200I
"
TSC2200I
"
TSC2200IPW
TSC2200IPWR
TSC2200IRHB
TSC2200IRHBR
Rails, 50
Tape and Reel, 2000
Tubes, 72
Tape and Reel, 2500
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
TIMING DIAGRAM
All specifications typical at
–
40
°
C to +85
°
C, +V
DD
= +2.7V.
t
td
t
Lag
t
dis
t
Lead
t
sck
t
wsck
t
wsck
t
hi
t
su
t
ho
t
a
t
v
t
r
t
f
SS
SCLK
MSB OUT
MSB IN
LSB IN
LSB OUT
BIT 6 ... 1
BIT 6 ... 1
MISO
MOSI
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Period
Enable Lead Time
Enable Lag Time
Sequential Transfer Delay
Data Setup Time
Data Hold Time (inputs)
Data Hold Time (outputs)
Slave Access Time
Slave D
OUT
Disable Time
Data Valid
Rise Time
Fall Time
t
sck
t
Lead
t
Lag
t
td
t
su
t
hi
t
ho
t
a
t
dis
t
v
t
r
t
f
30
15
15
30
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
15
10
30
30
TIMING CHARACTERISTICS
(1)(2)
At
–
40
°
C to +85
°
C, +V
DD
= +2.7V, V
REF
= +2.5V, unless otherwise noted.
TSC2200
NOTES: (1) All input signals are specified with t
r
= t
f
= 5ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. (2) See timing diagram below.
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