參數(shù)資料
型號(hào): TSC80251G2D-L16CB
廠商: Atmel
文件頁(yè)數(shù): 63/77頁(yè)
文件大?。?/td> 0K
描述: IC MCU 8BIT 16MHZ LO VOLT 44PLCC
標(biāo)準(zhǔn)包裝: 27
系列: 8x251
核心處理器: C251
芯體尺寸: 8/16-位
速度: 16MHz
連通性: EBI/EMI,I²C,Microwire,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器類型: ROMless
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
66
AT/TSC8x251G2D
4135F–8051–11/06
Maximum Total IOL for all:Output Pins71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test
conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports
1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change
from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address
lines are stabilizing.
4. Typical values are obtained using VDD = 3 V and TA = 25°C. They are not tested and there is not guarantee on these values.
5. The input threshold voltage of SCL and SDA meets the TWI specification, so an input voltage below 0.3VDD will be recog-
nized as a logic 0 while an input voltage above 0.7VDD will be recognized as a logic 1.
Figure 29.
IDD/IDL Versus XTAL Frequency; VDD = 2.7 to 3.6 V
Note:
1.The clock prescaler is not used: FOSC = FXTAL.
I
DD, IDL and IPD Test Conditions
Figure 30.
IDD Test Condition, Active Mode
max Active mode (mA)
typ Active mode (mA)
max Idle mode (mA)
typ Idle mode (mA)
15
10
5
0
IDD/IDL
(mA
)
Frequency at XTAL(1) (MHz)
24
68
14
10
12
16
VDD
XTAL2
VDD
Clock Signal
RST
VSS
TSC80251G2D
EA#
XTAL1
VDD
P0
(NC)
IDD
VDD
All other pins are unconnected
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