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參數(shù)資料
| 型號(hào)： | TSC87C51-12CB |
| 英文描述： | Introduction to TSC87C51/C52 OTP Microcontrollers |
| 中文描述： | 檢察官辦公室介紹TSC87C51/C52微控制器 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 80K |
| 代理商： | TSC87C51-12CB |
TSC87C51/52
5
MATRA
MHS
Rev. A
–
10 September 1997
Glossary
Power off Flag
This
flag is used by the software to make the dif
ference between a power on reset and a
reset exiting from power down.
In
the power down mode, the crystal is stopped and the microcontroller power consumption is closed to zero. This
flag
is useful for low power application using the power down mode.
Enhanced Timer 2
Two new features are added to the timer 2 :
Configuration as an up/down counter
Clock out generation
UART : Automatic Address Recognition
Two
new features are added to the UAR
T. These features lower the software task during multi mode operation :
Automatic
Address Recognition ; in this mode the address recognition is done by hardware rather than by software.
Framing error Detection; a new bit warn the software that one stop bit is missing.
Power–Down output using external interrupt
With this feature an external interrupt can cause a recover from power down mode ; otherwise, only a reset can restart
the microcontroller. this feature provides more flexibility for low power systems.
ALE disabling
The
“Address Latch Enable” is activated at a constant
rate of 1/6 the oscillator frequency
, except during an external data
memory
access at which one ALE pulse is skipped. When no external RAM and ROM access is required, the ALE is not
necessary and can generated noise and EMI. With the ALE disable, this signal is only generated under software when
it is required.
ONCE mode
The ON–Circuit Emulation (ONCE) mode facilitates testing and debugging of the system using the microcontroller
without having to remove the device from the circuit. In this mode, the device is placed on an inactive state and an
emulator or test CPU can be used to drive the circuit.
EPROM lock bits
The program lock bits protect the program memory from software piracy.
Four levels interrupt priority
The initial 8051 architecture has two levels interrupt priority. A second Interrupt Priority register has been added,
increasing the number of priority levels to four. This feature provides more flexibility to real time systems.
Full Static Design
This allows to reduce the system power consumption by bringing the clock frequency down to any value, even 0 Mhz
(DC), without loss of data.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSC87C51-16CA | Introduction to TSC87C51/C52 OTP Microcontrollers |
| TSC87C51-16CB | Introduction to TSC87C51/C52 OTP Microcontrollers |
| TSC87C5X | Introduction to TSC87C51/C52 OTP Microcontrollers |
| TSC87C51-25MKMQ | CMOS 0 to 25 MHz Programmable 8-bit Microcontroller |
| TSC87C52-12CBB | CMOS 0 to 33 MHz Programmable 8朾it Microcontroller |
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