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參數(shù)資料
| 型號： | TSC87C52-12CBB |
| 英文描述： | CMOS 0 to 33 MHz Programmable 8朾it Microcontroller |
| 中文描述： | 的CMOS 0至33 MHz的可編程微控制器8朾它 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 273K |
| 代理商： | TSC87C52-12CBB |
TSC87C52
16
Rev. C – 10 Sept 1997
Preliminary
MATRA MHS
DC Parameters for Low Voltage, commercial and industrial temperature range
T
A
= 0
°
C to +70
°
C; VSS = 0V; VCC = 2.7V to 5V
±
10%; F = 0 to 16 MHz.
T
A
= –40
°
C to +85
°
C; VSS = 0V; VCC = 2.7V to 5V
±
10%; F = 0 to 16 MHz.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIL
Input Low Voltage
–0.5
0.2 VCC – 0.1
V
VIH
Input High Voltage except XTAL1, RST
0.2 VCC + 0.9
VCC + 0.5
V
VIH1
Input High Voltage, XTAL1, RST
0.7 VCC
VCC + 0.5
V
VOL
Output Low Voltage, ports 1, 2, 3
(6)
0.45
V
IOL = 0.8mA
(4)
VOL1
Output Low Voltage, port 0, ALE, PSEN
(6)
0.45
V
IOL = 1.6mA
(4)
VOH
Output High Voltage, ports 1, 2, 3
0.9 VCC
V
IOH = –10
μ
A
VOH1
Output High Voltage, port 0, ALE, PSEN
0.9 VCC
V
IOH = –40
μ
A
IIL
Logical 0 Input Current ports 1, 2 and 3
–50
μ
A
Vin = 0.45V
ILI
Input Leakage Current
±
10
μ
A
0.45 < Vin < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3
–650
μ
A
Vin = 2.0V
RRST
RST Pulldown Resistor
50
90
(5)
200
k
CIO
Capacitance of I/O Buffer
10
pF
fc = 1MHz, T
A
= 25
°
C
IPD
Power Down Current
TBD
(5)
TBD
μ
A
VCC = 2.0V to 5.5V
(3)
ICC
Power Supply Current
(7)
Active Mode 16MHz
Idle Mode 16MHz
TBD
(5)
TBD
(5)
TBD
TBD
mA
mA
VCC = 3.3V
(1)
VCC = 3.3V
(2)
Notes for DC Electrical Characteristics
1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 13), VIL = VSS + 0.5V,
VIH = VCC – 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see NO TAG).
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC–0.5V; XTAL2
N.C; Port 0 = VCC; EA = RST = VSS (see Figure 11).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see NO TAG).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due
to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not neces-
sary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.
6. Under steady state (non–transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
Maximum IOL per 8–bit port:
10 mA
Port 0:
Ports 1, 2 and 3:
26 mA
15 mA
71 mA
Maximum total IOL for all output pins:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condi-
tions.
7. For other values, please contact your sales office.
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