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參數(shù)資料
| 型號(hào)： | TSC87C52-25MIMQ |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 25 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | CERAMIC, QPJ-44 |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 182K |
| 代理商： | TSC87C52-25MIMQ |
TSC87C52
16
Rev. E – July 03, 2000
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due
to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not neces-
sary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.
6. Under steady state (non–transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10 mA
Maximum IOL per 8–bit port:
Port 0:
26 mA
Ports 1, 2 and 3:
15 mA
Maximum total IOL for all output pins:
71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condi-
tions.
7. For other values, please contact your sales office.
VCC
ICC
(NC)
CLOCK
SIGNAL
VCC
All other pins are disconnected.
RST
XTAL2
XTAL1
VSS
VCC
P0
EA
Figure 10 ICC Test Condition, Active Mode
RST
EA
XTAL2
XTAL1
VSS
VCC
ICC
(NC)
P0
VCC
All other pins are disconnected.
CLOCK
SIGNAL
Figure 11 ICC Test Condition, Idle Mode
RST
EA
XTAL2
XTAL1
VSS
VCC
ICC
(NC)
P0
VCC
All other pins are disconnected.
Figure 12 ICC Test Condition, Power Down Mode
VCC–0.5V
0.45V
0.7VCC
0.2VCC–0.1
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
Figure 13 Clock Signal Waveform for ICC Tests in
Active and Idle Modes
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