參數(shù)資料
型號: TSI107D-100JE
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/2頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE 32BIT 503BGA
標(biāo)準(zhǔn)包裝: 24
系列: Tsi107™
應(yīng)用: 主機(jī)電橋
接口: PCI
電源電壓: 2.5V, 3.3V
封裝/外殼: 503-BBGA
供應(yīng)商設(shè)備封裝: 503-FCPBGA(33x33)
包裝: 托盤
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 1250 (CN2011-ZH PDF)
其它名稱: 800-1908
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October 26, 2009
2009 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Device Overview
The IDT Tsi107 Host Bridge for PowerPC provides system interconnect
between PowerPC processors, PCI peripherals, and local memory. PCI
support allows system designers to design systems quickly using
peripherals already developed for PCI and the other standard interfaces
available in the personal computer hardware environment.
The Tsi107 provides many of the other necessities for embedded appli-
cations, including a high-performance memory controller and dual-
processor support; two-channel flexible DMA controller; an interrupt
controller; an I2O-ready message unit; an inter-integrated circuit
controller (I2C); and low-skew clock drivers. The Tsi107 contains an
Embedded Programmable Interrupt Controller (EPIC) featuring five
hardware interrupts (IRQs), as well as 16 serial interrupts and four
timers. The Tsi107 uses an advanced, 2.5V CMOS process technology,
and is fully compatible with TTL devices.
Block Diagram
Multiprocessor and Local Bus Slave Support
The Tsi107 supports a programmable interface to microprocessors
implementing the PowerPC architecture, operating at bus frequencies
up to 133 MHz. The Tsi107 processor interface allows for a variety of
system configurations by providing support for a second processor and
a local bus slave.
Peripheral
Logic Block
Central
Control Unit
Memory/
ROM/
Port X
Control/
Address
32/64-bit Data and 32-bit Address
66-133 MHz
IEEE1149.1
Boundry
Scan
Five IRQs/
16 Serial
Interrupts
Master/
Slave
Data Bus
(32/64-bit)
with 8-bit
Parity or
ECC
Memory
Contr
oller
PCI Bus
Clocks
32-bit, up to 66 MHz
PCI Bus (Rev. 2.1)
Five Request/
Grant Pairs
80C2000_BK001_02
Processor Interface
PCI Interface
Arbiter
I2C
JTAG
Message
Unit
(I2O)
PLL
Memory
Data Path
DMA
DLL
Fan Out
Buffers
SDRAM
and CPU
Clocks
Timers
EPIC
Interrupt
Controller
Integrated Memory Controller
The memory interface controls processor and PCI interactions to main
memory. It supports a variety of programmable DRAM (FPM, EDO),
SDRAM, and ROM/Flash ROM configurations. These support timing at
speeds of up to 133 MHz.
PCI Bus Support
The Tsi107 PCI interface is designed to connect the processor and
memory buses to the PCI local bus without the need for “glue” logic. It
runs at speeds up to 66 MHz. The Tsi107 acts as either a master or
target on the PCI bus and contains a PCI bus arbitration unit which
reduces the need for an equivalent external unit. This reduces the total
system complexity and cost.
Features
Processor Interface
Supports the Motorola MPC603e, MPC7xx, and MPC74xx
processors
Supports the IBM PowerPC 603e, and PowerPC 7xx processors
Processor bus frequency up to 133 MHz
64/32-bit data bus, 32-bit address bus
I/O voltage: 2.5V or 3.3V
SMP support for a second processor
Full memory coherency, integrated arbiter and slave peripheral
support
Memory Interface
High-bandwidth (32-bit/64-bit) data bus up to 133 MHz
Programmable timing: supports either DRAM (FPM, EDO) or
SDRAM
Supports one to eight banks: 4, 16, 64, 128, and/or 256-bit
DRAMs/SDRAMs
1 GB RAM space, 144 MB ROM space
8, 32, or 64-bit ROM/Flash ROM
8, 32, or 64-bit general-purpose I/O port: uses ROM controller
interface with address strobe
Supports parity, read-modify-write, or error-correcting code (ECC)
PCI Interface
Compliant with PCI specification, (revision 2.1)
32-bit PCI interface — up to 66 MHz
5.0 V compatible
Read and write buffers to improve PCI performance
Selectable big or little-endian operation
PCI interface acts as host or agent — allows multiple Tsi107s on
one PCI bus
Tsi107 Host Bridge for PowerPC
Product Brief
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