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參數(shù)資料
| 型號(hào)： | TSM101CDT |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大?。?/td> | 55K |
| 代理商： | TSM101CDT |
TSM100
3/5
OPERATIONAL AMPLIFIER
V
CC
+
= +5V, V
CC
= Ground, V
o
= 1.4V,T
amb
= 25°C (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
io
Input Offset Voltage
T
amb
= 25°C
T
min.
≤
T
amb
≤
T
max.
Input Offset Voltage Drift
Input Offset Current
Input Bias Current
Large Signal Voltage Gain
V
CC
= 15V, R
L
= 2k, Vo = 1.4V to 11.4V
Supply Voltage Rejection Ratio
V
CC
= 5V to 30V
Input Common Mode Voltage Range
V
CC
= +30V - see note
1)
Common Mode Rejection Ratio
Output Current Source
V
CC
= +15V, Vo = 2V, V
id
= +1V
Short Circuit to Ground
V
CC
= +15V
Output Current Sink
V
id
= -1V,
V
CC
= +15V, V
o
= 2V
V
CC
= +15V, V
o
= 0.2V
High Level Output Voltage
V
CC
+
= 30V
T
amb
= 25°C, R
L
= 2k
T
amb
= 25°C, R
L
= 10k
Low Level Output Voltage
R
L
= 10k
Slew Rate at Unity Gain
V
i
= 0.5 to 3V, V
CC
= 15V
R
L
= 2k, C
L
= 100pF, unity gain
Gain Bandwidth Product
V
CC
= 30V,R
L
= 2k, C
L
= 100pF
f = 100kHz, V
in
= 10mV
Total Harmonic Distortion
f = 1kHz
A
V
= 20dB,R
L
= 2k, V
CC
= 30V
C
L
= 100pF, V
o
= 2V
pp
Equivalent Input Noise Voltage
f = 1kHz, Rs = 100
Vcc = 30V
0.5
3
4
mV
DV
io
I
io
I
ib
Avd
7
2
μ
V/°C
nA
nA
V/mV
30
150
20
50
100
SVR
65
100
dB
Vicm
1. The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of
the common-mode voltage range is V
CC+
- 1.5V.
But both inputs can go to Vcc+ +0.3V without damage.
0
(V
CC
+
) -1.5
V
CMR
I
source
65
85
dB
mA
20
40
I
o
40
60
mA
I
sink
10
12
20
50
mA
μA
V
OH
26
27
27
28
V
V
OL
5
15
mV
SR
0.2
0.4
V/
μ
s
GBP
0.5
0.9
MHz
THD
0.015
%
e
n
40
nV/
√
Hz
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