- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365987 > TSPC106AMG83CE MEMORY CONTROLLER PDF資料下載
參數(shù)資料
| 型號： | TSPC106AMG83CE |
| 英文描述： | MEMORY CONTROLLER |
| 中文描述： | 內(nèi)存控制器 |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 569K |
| 代理商： | TSPC106AMG83CE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
16
TSPC106
2102B
–
HIREL
–
02/02
PCI Interface Signals
Table 7 lists the PCI interface signals and provides a brief description of their functions.
Note that the bits in Table 7 are referenced in little-endian format.
The PCI specification defines a sideband signal as any signal, not part of the PCI speci-
fication, that connects two or more PCI-compliant agent, and has meaning only to those
agents. The TSPC106 implements four PCI sideband signals -FLSHREQ,
ISA_MASTER, MEMACK and PIRQ.
Table 7.
PCI Interface Signals
Signal
Signal Name
Number of
Pins
I/O
Signal Description
AD[31:0]
Address/data
32
I/O
Represents the physical address during the address phase of a
transaction. During the data phase(s) of a PCI transaction, AD[31:0]
contain data. AD[7:0] define the least significant byte and AD[31:24]
the most significant byte.
C/BE[3:0]
Command/byte
enable
4
O
During the address phase, C/BE[3:0] define the PCI bus command.
During the data phase, C/BE[3:0] are used as byte enables. Byte
enables determine which byte lanes carry meaningful data. C/BE0
applies to the least significant byte.
I
During the address phase, C/BE[3:0] indicates the PCI bus command
that another master is sending. During the data phase C/BE[3:0]
indicate which byte lanes are valid.
DEVSEL
Device select
1
O
Indicates that the TSPC106 has decoded the address and is the target
of the current access.
I
Indicates that some PCI agent (other than the TSPC106) has decoded
its address as the target of the current access.
FLSHREQ
Flush request
1
I
Indicates that a device needs to have the TSPC106 flush all of its
current operations.
FRAME
Frame
1
O
Indicates that the TSPC106, acting as a PCI master, is initiating a bus
transaction.
I
Indicates that another PCI master is initiating a bus transaction.
GNT
PCI bus grant
1
I
Indicates that the TSPC106 has been granted control of the PCI bus.
Note that GNT is a point-to-point signal. Every master has its own GNT
SIGNAL.
IRDY
Initializer ready
1
O
Indicates that the TSPC106, acting as a PCI master, can complete the
current data phase of a PCI transaction. During a write, the TSPC106
asserts IRDY to indicate that valid data is present on AD[31:0]. During
a read, the TSPC106 asserts IRDY to indicate that it is prepared to
accept data.
I
Indicates another PCI master is able to complete the current data
phase of the transaction.
ISA_
MASTER
ISA master
1
I
Indicates that an ISA master is requesting system memory.
LOCK
Lock
1
I
Indicates that a master is requesting exclusive access to memory,
which may require multiple transactions to complete.
MEMACK
Memory
acknowledge
1
O
Indicates that the TSPC106 has flushed all of its current operations
and has blocked all 60x transfers except snoop copy-back operations.
The TSPC106 asserts MEMACK in response to assertion of
FLSHREQ after the flush is complete.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSPC106AMG83CG | MEMORY CONTROLLER |
| TSPC106AVG66CE | MEMORY CONTROLLER |
| TSPC106AVG66CG | MEMORY CONTROLLER |
| TSPC106AVG83CE | MEMORY CONTROLLER |
| TSPC106AVG83CG | MEMORY CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSPC106AMG83CG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| TSPC106AMGB/Q66CE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| TSPC106AMGB/Q66CG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| TSPC106AMGB/Q83CE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| TSPC106AMGB/Q83CG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。