3
TSPC750A/740A
2128A–HIREL–01/02
GeneralParameters
Thegeneralparametersofthe750A/740Aarethefollowing:
Features
ExceptL2cacheinterfacethatisnotsupportedbythePowerPCversion,themajorfea-
turesimplementedinthePowerPC750Aarchitectureareasfollows:
Level2(L2)CacheInterface
(notimplementedon
TSPC740A)
InternalL2cachecontrollerand4K-entrytags;externaldataSRAMs
256K,512K,and1-Mbyte2-waysetassociativeL2cachesupport
Copy-backorwrite-throughdatacache(onapagebasis,orforallL2)
64-byte(256K/512K)and128-byte(1-Mbyte)sectoredlinesize
Supportsflow-through(reg-buf)synchronousburstSRAMs,pipelined(reg-reg)
synchronousburstSRAMs,andpipelined(reg-reg)late-writesynchronousburst
SRAMs
Core-to-L2frequencydivisorsof
÷
1,
÷
1.5,
÷
2,
÷
2.5,and
÷
3supported
BranchProcessingUnit
Fourinstructionsfetchedperclock
Onebranchprocessedpercycle(plusresolving2speculations)
Upto1speculativestreaminexecution,1additionalspeculativestreaminfetch
512-entrybranchhistorytable(BHT)fordynamicprediction
64-entry,4-waysetassociativebranchtargetinstructioncache(BTIC)tominimize
branchdelayslots
DispatchUnit
Fullhardwaredetectionofdependencies(resolvedintheexecutionunits)
Dispatchtwoinstructionstosixindependentunits(system,branch,load/store,fixed-
pointunit1,fixed-pointunit2,orfloating-point)
Serializationcontrol(predispatch,postdispatch,executionserialization)
Load/StoreUnit
Onecycleloadorstorecacheaccess(byte,half-word,word,double-word)
Effectiveaddressgeneration
Hitsundermisses(oneoutstandingmiss)
Single-cyclemisalignedaccesswithindoublewordboundary
Alignment,zeropadding,signextendforintegerregisterfile
Floating-pointinternalformatconversion(alignment,normalization)
Sequencingforload/storemultiplesandstringoperations
Storegathering
CacheandTLBinstructions
Technology
DieSize
TransistorCount
LogicDesign
PackagesL2
0.29mmCMOS,five-layermetal
7.56mmx8.79mm(67mm
2
)
6.35million
Fully-static
740A:Surfacemount255ceramicballgridarray(CBGA)andcolumninterposerceramicgrid
arrayCI-CGAwithoutL2interface
750A:Surfacemount360ceramicballgridarray(CBGA)andcolumninterposerceramicgrid
arrayCI-CGAwithL2interface
2.6V±
100mV
3.3V±
5%V
DC
CorePowerSupply
I/OPowerSupply