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參數(shù)資料
| 型號： | TSXPC603RMG14LC |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷 |
| 文件頁數(shù)： | 30/42頁 |
| 文件大小： | 961K |
| 代理商： | TSXPC603RMG14LC |
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TSPC603R
2125A–12/01
Cache coherency is enforced by on-chip bus snooping logic. Since the 603r’s data cache tags
are single ported, a simultaneous load or store and snoop access represent a resource con-
tention. The snoop access is given first access to the tags. The load or store then occurs on
the clock following snoop.
Figure 14.
Data Cache Organization
Exception Model
The following subsections describe the PowerPC exception model and the 603r implementa-
tion, respectively.
PowerPC Exception Model
The PowerPC exception mechanism allows the processor to change to supervisor state as a
result of external singles, errors, or unusual conditions arising in the execution of instructions,
and differ from the arithmetic exceptions defined by the IEEE for floating-point operations.
When exceptions occur, information about the state of the processor is saved to certain regis-
ters and the processor begins execution at an address (exception vector) predetermined for
each exception. Processing of exceptions occurs in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more specific
condition may be determined by examining a register associated with the exception - for
example, the DSISR and the FPSCR. Additionally, some exception conditions can be explicitly
enable or disabled by software.
The PowerPC architecture requires that exceptions be handled in program order; therefore,
although a particular implementation may recognize exception conditions out of order, they
are presented strictly in order. When an instruction-caused exception is recognized, any unex-
ecuted instructions that appear earlier in the instruction stream, including any that have not yet
entered the execute state, are required to complete before the exception is taken. Any excep-
tions caused by those instructions are handled first. Likewise, exceptions that are
asynchronous and precise are recognized when they occur, but are not handled until the
instruction currently in the completion state successfully completes execution or generates an
exception, and the completed store queue is emptied.
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