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參數(shù)資料
| 型號： | TSXPC603RMGS10LC |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷 |
| 文件頁數(shù)： | 24/42頁 |
| 文件大?。?/td> | 961K |
| 代理商： | TSXPC603RMGS10LC |
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24
TSPC603R
2125A–12/01
(mfspr) instructions) or implicit, as the part of the execution of an instruction. Some registers
are accessed both explicitly and implicitly.
Il the 603r, all SPRs are 32 bits wide.
USER-LEVEL SPRs:
The following 603r SPRs are accessible by user-level software:
Link register (LR) - The link register can be used to provide the branch target address and
to hold the return address after branch and link instructions. The LR is 32 bits wide in
32-bit implementations.
Count register (CTR) - The CRT is decremented and tested automatically as a result of
branch-and-count instructions. The CTR is 32 bits wide in 32-bit implementations.
Integer exception register (XER) - The 32-bit XER contains the summary overflow bit,
integer carry bit, overflow bit, and a field specifying the number of bytes to be transferred
by a Load String Word Indexed (lswx) or Store String Word Indexed (stswx) instruction.
SUPERVISOR-LEVEL SPRs:
The 603r also contains SPRs that can be accessed only by
supervisor-level software. These registers consist of the following:
The 32-bit DSISR defines the cause of data access and alignment exceptions.
The data address register (DAR) is a 32-bit register that holds the address of an access
after an alignment or DSI exception.
Decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism
for causing a decrementer exception after a programmable delay.
The 32-bit SDR1 specifies the page table format used in virtual-to-physical address
translation for pages. (Note that physical address is referred to as real address in the
architecture specification).
The machine status save/restore register 0 (SRR0) is a 32-bit register that is used by the
603r for saving the address of the instruction that caused the exception, and the address
to return to when a Return from Interrupt (
rfi
) instruction is executed.
The machine status save/restore register 1 (SRR1) is a 32-bit register used to save
machine status on exceptions and to restore machine status when an
rfi
instruction is
executed.
The 32-bit SPRG0-SPRG3 registers are provided for operating system use.
The external access register (EAR) is a 32-bit register that controls access to the external
control facility through the External Control In Word Indexed (
eciwx
) and External Control
Out Word Indexed (
ecowx
) instructions.
The time base register (TB) is a 64-bit register that maintains the time of day and operates
interval timers. The TB consists of two 32-bit fields - time base upper (TBU) and time base
lower (TBL).
The processor version register (PVR) is a 32-bit, read-only register that identifies the
version (model) and revision level of the PowerPC processor.
Block address translation (BAT) arrays - The PowerPC architecture defines 16 BAT
registers, divided into four pairs of data BATs (DBATs) and four pairs of instruction BATs
(IBATs). See Figure 13 for a list of the SPR numbers for the BAT arrays.
The following supervisor-level SPRs are implementation-specific to the 603r:
The DMISS and IMISS registers are read-only registers that are loaded automatically
upon an instruction or data TLB miss.
The HASH1 and HASH2 registers contain the physical addresses of the primary and
secondary page table entry groups (PTEGs).
The ICMP and DCMP registers contain a duplicate of the first word in the page table entry
(PTE) for which the table search is looking.
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