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參數(shù)資料
| 型號： | TSXPC603RMGS12LC |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷 |
| 文件頁數(shù)： | 34/42頁 |
| 文件大?。?/td> | 961K |
| 代理商： | TSXPC603RMGS12LC |
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34
TSPC603R
2125A–12/01
Memory Management
The following subsections describe the memory management features of the PowerPC archi-
tecture, and the 603r implementation, respectively.
PowerPC Memory Management
The primary functions of the MMU are to translate logical (effective) addresses to physical
addresses for memory accesses, and to provide access protection on blocks and pages of
memory.
There are two types of accesses generated by the 603r that require address translation—
instruction accesses, and data accesses to memory generated by load and store instructions.
The PowerPC MMU and exception model support demand-paged virtual memory. Virtual
memory management permits execution of programs larger than the size of physical memory;
demand-paged implies that individual pages are loaded into physical memory from system
memory only when they are first accessed by an executing program.
The hashed page table is a variable-sized data structure that defines the mapping between
virtual page numbers and physical page numbers. The page table size is a power of 2, and its
starting address is a multiple of its size.
The page table contains a number of page table entry groups (PTEGs). A PTEG contains
eight page table entries (PTEs) of eight bytes each; therefore, each PTEG is 64 bytes long.
PTEG addresses are entry points for table search operations.
Address translations are enabled by setting bits in the MSR-MSR[IR] enables instruction
address translations and MSR[DR] enables data address translations.
PowerPC 603r Microprocessor Memory Management
The instruction and data memory management units in the 603r provide 4G byte of logical
address space accessible to supervisor and user programs with a 4K byte page size and
256M byte segment size. Block sizes range from 128K byte to 256M byte and are software
selectable. In addition, the 603r uses an interim 52-bit virtual address and hashed page tables
for generating 32-bit physical addresses. The MMUs in the 603r rely on the exception process-
ing mechanism for the implementation of the paged virtual memory environment and for
enforcing protection of designated memory areas.
Instruction and data TLBs provide address translation in parallel with the on-chip cache
access, incurring no additional time penalty in the event of a TLB hit. A TLB is a cache of the
most recently used page table entries. Software is responsible for maintaining the consistency
of the TLB with memory. The 603r’s TLBs are 64-entry, two-way set-associative caches that
contain instruction and data address translations. The 603r provides hardware assist for soft-
ware table search operations through the ashed page table on TLB misses. Supervisor
software can invalidate TLB entries selectively.
Instruction address
breakpoint
01300
An instruction address breakpoint exception occurs when the address (bits 0-29) in the
IABR matches the next instruction to complete in the completion unit, and the IABR enable
bit (bit 30) is set to 1.
System
management
interrupt
01400
A system management interrupt is caused when MSR[EE] = 1 and the SMI input signal is
asserted.
Reserved
01500–02FFF
—
Table 15.
Exceptions and Conditions (Continued)
Exception Type
Vector Offset
(hex)
Causing Conditions
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