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參數(shù)資料
| 型號： | TSXPC603RMGS14LC |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷 |
| 文件頁數(shù)： | 13/42頁 |
| 文件大?。?/td> | 961K |
| 代理商： | TSXPC603RMGS14LC |
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13
TSPC603R
2125A–12/01
Note that the 603r cannot switch from on power management mode to another without first
returning to full on mode. The nap and sleep modes disable bus snooping; therefore, a hard-
ware handshake is provided to ensure coherency before the 603r enters these power
management modes. Table 7 summarizes the four power states.
Note:
1. Exceptions are referred to as interrupts in the architecture specification
Power Management Modes
The following sections describe the characteristics of the 603r’s power management modes,
the requirements for entering and exiting the various modes, and the system capabilities pro-
vided by the 603r while the power management modes are active.
FULL-POWER MODE WITH DPM DISABLED:
Full-power mode with DPM disabled power
mode is selected when the DPM enable bit (bit 11) in HID0 is cleared.
Default state following power-up and HRESET.
All functional units are operating at full processor speed at all times.
FULL-POWER MODE WITH DPM ENABLED:
Full-power mode with DPM enabled (HID0[11]
= 1) provides on-chip power management without affecting the functionality or performance of
the 603r.
Required functional units are operating at full processor speed.
Functional units are clocked only when needed.
No software or hardware intervention required after mode is set.
Software/hardware and performance transparent.
DOZE MODE:
Doze mode disables most functional units but maintains cache coherency by
enabling the bus interface unit and snooping. A snoop hit will cause the 603r to enable the
data cache, copy the data back to memory, disable the cache, and fully return to the doze
state.
Most functional units disabled.
Bus snooping and time base/decrementer still enabled.
Dose mode sequence:
- Set doze bit (HID0[8) = 1).
- 603r enters doze mode after several processor clocks.
Several methods of returning to full-power mode:
- Assert INT, SMI, MCP or decrementer interrupts.
- Assert hard reset or soft reset.
Table 7.
Power PC 603r Microprocessor Programmable Power Modes
PM Mode
Functioning Units
Activation Method
Full-Power Wake Up Method
Full Power
All units active
—
—
Full Power (with DPM)
Requested logic by demand
By instruction dispatch
—
Doze
- Bus snooping
- Data cache as needed
- Decrementer timer
Controlled by SW
External asynchronous exceptions
(1)
Decrementer interrupt
Reset
Nap
Decrementer timer
Controlled by hardware and
software
External asynchronous exceptions
Decrementer interrupt
Reset
Sleep
None
Controlled by hardware and
software
External asynchronous exceptions
Reset
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