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| 型號(hào)： | TSXPC603RMGU8LC |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷 |
| 文件頁數(shù)： | 32/42頁 |
| 文件大?。?/td> | 961K |
| 代理商： | TSXPC603RMGU8LC |
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32
TSPC603R
2125A–12/01
Although exceptions have other characteristics as well, such as whether they are maskable or
non maskable, the distinctions shown in Table 14 define categories of exceptions that the 603r
handles uniquely. Note that Table 14 includes no synchronous imprecise instructions. While
the PowerPC architecture supports imprecise handling of floating-point exceptions, the 603r
implements these exception modes as precise exceptions.
The 603r’s exceptions, and conditions that cause them, are listed in Table 15. Exceptions that
are specific to the 603r are indicated.
Table 14.
PowerPC 603r Microprocessor Exception Classifications
Synchronous/Asynchronous
Precise/Imprecise
Exception Type
Asynchronous, Non Maskable
Imprecise
Machine check
System reset
Asynchronous, Maskable
Precise
External interrupt
Decrementer
System management interrupt
Synchronous
Precise
Instruction-caused exceptions
Table 15.
Exceptions and Conditions
Exception Type
Vector Offset
(hex)
Causing Conditions
Reserved
00000
—
System Reset
00100
A system reset is caused by the assertion of either SRESET or HRESET.
Machine Check
00200
A machine check is caused by the assertion of the TEA signal during a data bus
transaction, assertion of MCP, or an address or data parity error.
DSI
00300
The cause of a DSI exception can be determined by the bit settings in the DSISR, listed as
follows:
1 Set if the translation of an attempted access is not found in the primary hash table entry
group (HTEG), or in the rehashed secondary HTEG, or in the range of the DBAT register;
otherwise cleared.
4 Set if a memory access is not permitted by the page or DBAT protection mechanism;
otherwise cleared.
5 Set by an eciwx or ecowx instruction if the access is to an address that is marked as
write-through, or execution of a load/store instruction that accesses a direct-store segment.
6 Set for a store operation and cleared for a load operation.
11 Set if eciwx or ecowx is used and EAR[E] is cleared.
ISI
00400
An ISI exception is caused when an instruction fetch cannot be performed for any of the
following reasons:
The effective (logical) address cannot be translated. That is, there is a page fault for this
portion of the translation, so an ISI exception must be taken to load the PTE (and possibly
the page) into memory.
The fetch access violates memory protection. If the key bits (Ks and Kp) in the segment
register and the PP bits in the PTE are set to prohibit read access, instructions cannot be
fetched from this location.
External interrupt
00500
An external interrupt is caused when MSR[EE] = 1 and the INT signal is asserted.
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