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參數(shù)資料
| 型號： | TSXPC603RVG6LC |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷 |
| 文件頁數(shù)： | 40/42頁 |
| 文件大小： | 961K |
| 代理商： | TSXPC603RVG6LC |
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40
TSPC603R
2125A
–
12/01
System Design
Information
PLL Power Supply
Filtering
The A
V
dd
power signal is provided on the 603e to provide power to the clock generation
phase-locked loop. To ensure stability of the internal clock, the power supplied to the A
V
dd
input signal should be filtered using a circuit similar to the one shown in Figure 17. The circuit
should be placed as close to the A
V
dd
pin to ensure it filters out as much noise as possible.
The 0.1 μF capacitor should be closest to the A
V
dd
pin, followed by the 10 μF capacitor, and
finally the 10
resistor to
V
dd
. These traces should be kept short and direct.
Figure 17.
PLL Power Supply Filter Circuit
Decoupling
Recommendations
Due to the 603e
’
s dynamic power management feature, large address and data buses, and
high operating frequencies, the 603e can generate transient power surges and high frequency
noise in its power supply, especially while driving large capacitive loads. This noise must be
prevented from reaching other components in the 603e system, and the 603e itself requires a
clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each
V
dd
and O
V
dd
pin of the 603e. It is
also recommended that these decoupling capacitors receive their power from separate
V
dd
,
O
V
dd
, and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should vary in value from 220 pF to 10 μF to provide both high-and low-fre-
quency filtering, and should be placed as close as possible to their associated
V
dd
or O
V
dd
pin.
Suggested values for the
V
dd
pins 220 pF (ceramic), 0,01 μF (ceramic) and 0,1 μf (ceramic).
Suggested values for the O
V
dd
pins 0,01 μF (ceramic), 0,1 μF (ceramic), and 10 μF (tantalum).
Only SMT (surface mount technology) capacitors should be used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around
the PCB, feeding the
V
dd
and O
V
dd
planes, to enable quick recharging of the smaller chip
capacitors. These bulk capacitors should also have a low ESR (equivalent series resistance)
rating to ensure the quick response time necessary. They should also be connected to the
power and ground planes through two vias to minimize inductance. Suggested bulk capacitors
100 μF (AVX TPS tantalum) or 330 μf (AVX TPS tantalum).
Connection
Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appro-
priate signal level. Unused active low inputs should be tied to
V
dd
. Unused active high inputs
should be connected to GND. ALL NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external
V
dd
, O
V
dd
, and GND pins of the
603e.
Pull-up Resistor
Requirements
The 603e requires high-resistive (weak: 10 K
) pull-up resistors on several control signals of
the bus interface to maintain the control signals in the negated state after they have been
actively negated and released by the 603e or other bus master. These signals are: TS, ABB,
DBB, and ARTRY.
Vdd
AVdd
0.1
μ
F
10
μ
F
GND
10
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