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參數(shù)資料
| 型號(hào)： | TSXPC603RVGS14LC |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷 |
| 文件頁數(shù)： | 23/42頁 |
| 文件大?。?/td> | 961K |
| 代理商： | TSXPC603RVGS14LC |
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TSPC603R
2125A–12/01
Having access to privilege instructions, registers, and other resources allows the operating
system to control the application environment (providing virtual memory and protecting operat-
ing-system and critical machine resources). Instructions that control the state of the processor,
the address translation mechanism, and supervisor registers can be executed only when the
processor is operating in supervisor mode.
The following sections summarize the PowerPC registers that are implemented in the 603r.
General-Purpose Registers (GPRs)
The PowerPC architecture defines 32 user-level, general-purpose registers (GPRs). These
registers are either 32 bits wide in 32-bit PowerPC microprocessors and 64 bits wide in 64-bit
PowerPC microprocessors. The GPRs serve as the data source or destination for all integer
instructions.
Floating-Point Registers (FPRs)
The PowerPC architecture also defines 32 user-level, 64-bit floating-point registers (FPRs).
The FPRs serve as the data source or destination for floating-point instructions. These regis-
ters can contain data objects of either single- or double-precision floating-point formats.
Condition Register (CR)
The CR is a 32-bit user-level register that consists of eight four-bit fields that reflect the results
of certain operations, such as move, integer and floating-point compare, arithmetic, and logical
instructions, and provide a mechanism for testing and branching.
Floating-Point Status and Control Register (FPSCR)
The floating-point status and control register (FPSCR) is a user-level register that contains all
exception signal bits, exception summary bits, exception enable bits, and rounding control bits
needed for compliance with the IEEE 754 standard.
Machine State Register (MSR)
The machine state register (MSR) is a supervisor-level register that defines the state of the
processor. The contents of this register are saved when an exception is taken and restored
when the exception handling completes. The 603r implements the MSR as a 32-bit register,
64-bit PowerPC processors implement a 64-bit MSR.
Segment Registers (SRs)
For memory management, 32-bit PowerPC microprocessors implement sixteen 32-bit seg-
ment registers (SRs). To speed access, the 603r implements the segment registers as two
arrays; a main array (for data memory accesses) and a shadow array (for instruction memory
accesses). Loading a segment entry with the Move to Segment Register (stsr) instruction
loads both arrays.
Special-Purpose Registers (SPRs)
The powerPC operating environment architecture defines numerous special-purpose registers
that serve a variety of functions, such as providing controls, indicating status, configuring the
processor, and performing special operations. During normal execution, a program can
access the registers, shown in Figure 13, depending on the program’s access privilege (super-
visor or user, determined by the privilege-level (PR) bit in the MSR). Note that register such as
the GPRs and FPRs are accessed through operands that are part of the instructions. Access
to registers can be explicit (that is, through the use of specific instructions for that purpose
such as Move to Special-Purpose Register (mtspr) and Move from Special-Purpose Register
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