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參數(shù)資料
| 型號： | TSXPC603RVGS8LC |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷 |
| 文件頁數(shù)： | 8/42頁 |
| 文件大?。?/td> | 961K |
| 代理商： | TSXPC603RVGS8LC |
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8
TSPC603R
2125A–12/01
Table 4.
Signal index
Signal Name
Mnemonic
Signal function
Signal
type
Address Acknowledge
AACK
The address phase of a transaction is complete
Input
Address Bus Busy
ABB
If output, the 603r is the address bus master
If input, the address bus is in use
I/O
Address Bus Parity
AP[0-3]
If output, represents odd parity for each of 4 bytes of the physical address for a
transaction
If input, represents odd parity for each of 4 bytes of the physical address for
snooping operations
I/O
Address Parity Error
APE
Incorrect address bus parity detected on a snoop
Output
Address Retry
ARTRY
If output, detects a condition in which a snooped address tenure must be
retried
If input, must retry the preceding address tenure
I/O
Bus Grant
BG
May, with the proper qualification, assume mastership of the address bus
Input
Bus Request
BR
Request mastership of the address bus
Output
Cache Inhibit
Cl
A single-beat transfer will not be cached
Output
Test Clock
CLK_OUT
Provides PLL clock output for PLL testing and monitoring
Output
Checkstop Input
CKSTP_IN
Must terminate operation by internally gating off all clocks, and release all
outputs
Input
Checkstop Output
CKSTP_OUT
Has detected a checkstop condition and has ceased operation
Output
Cache Set Entry
CSE[0-1]
Cache replacement set element for the current transaction reloading into or
writing out of the cache
Output
Data Bus Busy
DBB
If output, the 603r is the data bus master
If input, another device is bus master
I/O
Data Bus Disable
DBDIS
(For a write transaction) must release data bus and the data bus parity to high
impedance during the following cycle
Input
Data Bus Grant
DBG
May, with the proper qualification, assume mastership of the data bus
Input
Data Bus Write Only
DBW0
May run the data bus tenure
Input
Data Bus Parity
DP[0-7]
If output, odd parity for each of 8 bytes of data write transactions
If input, odd parity for each byte of read data
I/O
Data Parity Error
DPE
Incorrect data bus parity
Output
Data Retry
DRTRY
Must invalidate the data from the previous read operation
Input
Global
GBL
If output, a transaction is global
If input, a transaction must be snooped by the 603r
I/O
Hard Reset
HRESET
Initiates a complete hard reset operation
Input
Interrupt
INT
Initiates an interrupt if bit EE of MSR register is set
Input
LSSD_MODE
LSSD test control signal for factory use only
Input
L1_TSTCLK
LSSD test control signal for factory use only
Input
L2_TSTCLK
LSSD test control signal for factory use only
Input
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