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| 型號： | TSXPC603RVGSU10LC |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷 |
| 文件頁數(shù)： | 28/42頁 |
| 文件大小： | 961K |
| 代理商： | TSXPC603RVGSU10LC |
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TSPC603R
2125A–12/01
Note that this grouping of the instructions does not indicate which execution unit executes a
particular instruction or group of instructions.
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions
operate on single-precision (one word) and double-precision (one double word) floating-point
operands. The PowerPC architecture uses instructions that are four bytes long and
word-aligned. It provides for byte, half-word, and word operand loads and stores between
memory and a set of 32 GPRs. It also provides for word and double-word operand loads and
stores between memory and a set of 32 floating-point registers (FPRs).
Computational instructions do not modify memory. To use a memory operand in a computa-
tion and then modify the same or another memory location, the memory contents must be
loaded into a register, modified, and then written back to the target location with distinct
instructions.
PowerPC processors follow the program flow when they are in the normal execution state.
However, the flow of instructions can be interrupted directly by the execution of an instruction
or by an asynchronous event. Either kind of exception may cause one of several components
of the system software to be invoked.
CALCULATING EFFECTIVE ADDRESSES:
The effective address (EA) is the 32-bit address
computed by the processor when executing a memory access or branch instruction or when
fetching the next sequential instruction.
The PowerPC architecture supports two simple memory addressing modes:
EA = (RA|0) + offset (including offset = 0) (register indirect with immediate index).
EA = (RA|0) + rB (register indirect with index).
These simple addressing modes allow efficient address generation for memory accesses. Cal-
culation of the effective address for aligned transfers occurs in a single clock cycle.
For a memory access instruction, if the sum of the effective address and the operand length
exceeds the maximum effective address, the memory operand is considered to wrap around
from the maximum effective address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit unsigned
binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations.
PowerPC 603r Microprocessor Instruction Set
The 603r instruction set is defined as follows:
The 603r provides hardware support for all 32-bit PowerPC instructions.
The 603r provides two implementation-specific instructions used for software table search
operations following TLB misses:
- Load Data TLB Entry (
tlbld
).
- Load Instruction TLB Entry (
tlbli
).
The 603r implements the following instructions which are defined as optional by the
PowerPC architecture :
- External Control In Word Indexed (
eciwx
).
- External Control Out Word Indexed (
ecowx
).
- Floating Select (
fsed
).
- Floating Reciprocal Estimate Single-Precision (
fres
).
- Floating Reciprocal Square Root Estimate (
frsqrte
).
- Store Floating-Point as Integer Word (
stfiwx
).
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