參數(shù)資料
型號： TSXPC750AVGS8LH
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 4/44頁
文件大?。?/td> 870K
代理商： TSXPC750AVGS8LH
4
TSPC750A/740A
2128A–HIREL–01/02
Big-andlittle-endianbyteaddressingsupported
Misalignedlittle-endiansupportinhardware
Fixed-pointUnits
Fixed-pointunit1(FXU1)-multiply,divide,shift,rotate,arithmetic,logical
Fixed-pointunit2(FXU2)-shift,rotate,arithmetic,logical
Single-cyclearithmetic,shift,rotate,logical
Multiplyanddividesupport(multi-cycle)
Earlyoutmultiply
BusInterface
Compatiblewith60xprocessorinterface
32-bitaddressbus
64-bitdatabus
Bus-to-corefrequencymultipliersof3x,3.5x,4x,4.5x,5x,5.5x,6x,6.5x,7x,7.5x,
8xsupported
Decode
Registerfileaccess
Forwardingcontrol
Partialinstructiondecode
Floating-pointUnit
SupportforIEEE-754standardsingle-anddouble-precisionfloating-pointarithmetic
3cyclelatency,1cyclethroughput,single-precisionmultiply-add
3cyclelatency,1cyclethroughput,double-precisionadd
4cyclelatency,2cyclethroughput,double-precisionmultiply-add
Hardwaresupportfordivide
Hardwaresupportfordenormalizednumbers
Timedeterministicnon-IEEEmode
SystemUnit
ExecutesCRlogicalinstructionsandmiscellaneoussysteminstructions
Specialregistertransferinstructions
CacheStructure
32K,32-byteline,8-waysetassociativeinstructioncache
32K,32-byteline,8-waysetassociativedatacache
Single-cyclecacheaccess
Pseudo-LRUreplacement
Copy-backorwrite-throughdatacache(onapageperpagebasis)
SupportsallPowerPCmemorycoherencymodes
Non-blockinginstructionanddatacache(oneoutstandingmissunderhits)
Nosnoopingofinstructioncache
MemoryManagementUnit
128entry,2-waysetassociativeinstructionTLB
128entry,2-waysetassociativedataTLB
HardwarereloadforTLBs
4instructionBATsand4dataBATs
Virtualmemorysupportforupto4hexabytes(2
52
)ofvirtualmemory
Realmemorysupportforupto4gigabytes(2
32
)ofphysicalmemory
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