參數(shù)資料
型號: TSXPC750AVGU12LE
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 28/44頁
文件大?。?/td> 870K
代理商: TSXPC750AVGU12LE
28
TSPC750A/740A
2128A–HIREL–01/02
Figure16showstheL2busoutputtimingdiagramsfortheTSPC750A.
Figure16.
L2BusOutputTimingDiagrams
IEEE1149.1ACTiming
Specifications
Table15providestheIEEE1149.1(JTAG)ACtimingspecificationsasdefinedinFigure
17,Figure18,Figure19,andFigure20.
Notes:
1. TRSTisanasynchronouslevelsensitivesignal.Thesetuptimeisfortestpurposesonly.
2. Non-JTAGsignalinputtimingwithrespecttoTCK.
3. Non-JTAGsignaloutputtimingwithrespecttoTCK.
4. Guaranteedbydesignandcharacterization.
27
VM
VM = Midpoint Voltage 1.4V)
L2SYNC_IN
26
ALL OUTPUTS
VM
28
L2DATA BUS
Table15.
JTAGACTimingSpecifications(IndependentofSYSCLK)
V
DD
=AV
DD
=L2AV
DD
=2.6V
DC
±
100mV,OV
DD
=L2OV
DD
=3.3±5%V
DC
,GND=0V
DC
,-55
T
j
<125
°
C,C
L
=50pF
Num
Characteristic
Min
Max
Unit
Notes
TCKFrequencyOfOperation
0
33.3
MHz
1
TCKCycleTime
30
-
ns
2
TCKClockPulseWidthMeasuredat1.4V
15
-
ns
3
TCKRiseandFallTimes
0
2
ns
4
SpecificationObsolete,IntentionallyOmitted
5
TRSTAssertTime
25
-
ns
1
6
Boundary-scanInputDataSetupTime
4
-
ns
2
7
Boundary-scanInputDataHoldTime
15
-
ns
2
8
TCKtoOutputDataValid
4
20
ns
3
9
TCKtoOutputHighImpedance
3
19
ns
3,4
10
TMS,TDIDataSetupTime
0
-
ns
11
TMS,TDIDataHoldTime
12
-
ns
12
TCKtoTDODataValid
4
12
ns
13
TCKtoTDOHighImpedance
3
9
ns
4
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