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參數(shù)資料
| 型號(hào)： | TU24C04BS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS I2C 2-WIRE BUS 4K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 512 X 8 BIT EEPROM |
| 中文描述： | 的CMOS的I2C 2線總線4K的電可擦除可編程ROM的512 × 8位EEPROM |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 48K |
| 代理商： | TU24C04BS |
24C04
PRODUCT INTRODUCTION
Turbo IC, Inc.
Note: The write cycle time t
WC
is the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle.
DESCRIPTION (Continued):
For a write operation, the master issues a start condition, a
device address byte, a memory address byte, and then up to
16 data bytes. The Turbo IC 24C04 acknowledges after each
byte transmission. To terminate the transmission, the master
issues a stop condition by pulling SDA from low to high while
SCL is high.
For a read operation, the master issues a start condition and
a device address byte. The Turbo IC 24C04 acknowledges,
and then transmits a data byte, which is accessed from the
EEPROM memory. The master acknowledges, indicating that
it requires more data bytes. The Turbo IC 24C04 transmits
more data bytes, with the memory address counter auto-
matically incrementing for each data byte, until the master
does not acknowledge, indicating that it is terminating the
transmission. The master then issues a stop condition.
DEVICE OPERATION:
BIDIRECTIONAL BUS PROTOCOL:
The Turbo IC 24C04 follows the I2C bus protocol. The proto-
col defines any device that sends data onto the SDA bus as
a transmitter, and the receiving device as a receiver. The
device controlling the transfer is the master and the device
being controlled is the slave. The master always initiates the
data transfers, and provides the clock for both transmit and
receive operations. The Turbo IC 24C04 acts as a slave de-
vice in all applications. Either the master or the slave can
take control of the SDA bus, depending on the requirement
of the protocol.
START/STOP CONDITION AND DATA TRANSITIONS:
While SCL clock is high, a high to low transition on the SDA
bus is recognized as a START condition which precedes any
read or write operation. While SCL clock is high, a low to
high transition on the SDA bus is recognized as a STOP con-
dition which terminates the communication and places the
Turbo IC 24C04 into standby mode. All other data transitions
on the SDA bus must occur while SCL clock is low to ensure
proper operation.
ACKNOWLEDGE:
All data is serially transmitted in bytes (8 bits) on the SDA
bus. The acknowledge protocol is used as a handshake sig-
nal to indicate successful transmission of a byte of data. The
bus transmitter, either the master or the slave (Turbo IC
24C04), releases the bus after sending a byte of data on the
SDA bus. The receiver pulls the SDA bus low during the ninth
clock cycle to acknowledge the successful transmission of a
byte of data. If the SDA is not pulled low during the ninth
clock cycle, the Turbo IC 24C04 terminates the data trans-
mission and goes into standby mode.
For the write operation, the Turbo IC 24C04 acknowledges
after the device address byte, acknowledges after the memory
address byte, and acknowledges after each subsequent data
byte.
For the read operation, the Turbo IC 24C04 acknowledges
after the device address byte. Then the Turbo IC 24C04 trans-
mits each subsequent data byte, and the master acknowl-
edges after each data byte transfer, indicating that it requires
more data bytes. The Turbo IC 24C04 monitors the SDA bus
for the acknowledge. To terminate the transmission, the mas-
ter does not acknowledge, and then sends a stop condition.
Write Cycle Timing
SCL
SDA
WORD n
8th BIT
ACK
STOP
CONDITION
START
CONDITION
tWC
2
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