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參數(shù)資料
| 型號： | TUA6010XS |
| 廠商： | SIEMENS A G |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | VIDEO TUNER, PDSO28 |
| 文件頁數(shù)： | 31/32頁 |
| 文件大小： | 839K |
| 代理商： | TUA6010XS |
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TUA 6010XS
Semiconductor Group
8
05.96
Data are exchanged between the processor and the PLL via the I2C Bus. The clock is
generated by the processor (input SCL), while pin SDA functions as an input or output
depending on the direction of the data (open collector, external pull-up resistor). Both
inputs have hysteresis and a lowpass characteristic, which enhance the noise immunity
of the I2CBus.
The data from the processor pass through an I2C Bus controller. Depending on their
function the data are subsequently stored in registers. If the bus is free, both lines will be
in the marking state (SDA, SCL are ‘HIGH’). Each telegram begins with the start
condition and ends with the stop condition. Start condition: SDA goes ‘LOW’, while SCL
remains ‘HIGH’. Stop condition: SDA goes ‘HIGH’ while SCL remains ‘HIGH’. All further
information transfer takes place during SCL = ‘LOW’, and the data is forwarded to the
control logic on the positive clock edge.
The table 1 ‘bit allocation’ should be referred to the following description. All telegrams
are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control
logic returns the SDA line to ‘LOW’ (acknowledge condition). The first byte is comprised
of seven address bits. These are used by the processor to select the PLL from several
peripheral components (chip select). The eighth bit (R/W) determines whether data are
written into (R/W = ‘0’) or read from (R/W = ‘1’) the PLL.
In the data portion of the telegram during a WRITE operation, the first bit of the first or
third data byte determines whether a divider ratio or control information is to follow. In
each case the second byte of the same data type or a stop condition has to follow the
first byte.
If the address byte indicates a READ operation, the PLL generates an acknowledge and
then shifts out the status byte onto the SDA line. lf the processor generates an
acknowledge, a further status byte is output; otherwise the data line is released to allow
the processor to generate a stop condition. The status word consists of two bits from the
TTL input ports, three bits from the A/D converter, the lock flag and the power ON flag.
Four different chip addresses can be set by appropriate connection of pin CAU (see
table 2 ‘a(chǎn)ddress selection’).
When the supply voltage is applied, a power-on reset circuit prevents the PLL from
setting the SDA line to ‘LOW’, which would block the bus. The power-on reset flag POR
is set at power-on and when
V
VCCD goes below 3.2 V. It will be reset at the end of a READ
operation.
相關PDF資料 |
PDF描述 |
|---|---|
| TUA6014-K | 2-BAND, VIDEO TUNER, PDSO28 |
| TUA6014-S | 2-BAND, VIDEO TUNER, PDSO28 |
| TUA6014XS | 2-BAND, VIDEO TUNER, PDSO28 |
| TUA6012XS | 2-BAND, VIDEO TUNER, PDSO28 |
| TUA6020 | 2-BAND, VIDEO TUNER, PDSO28 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TUA6012 | 制造商:SIEMENS 制造商全稱:Siemens Semiconductor Group 功能描述:Components for Entertainment Electronics |
| TUA6012XS | 制造商:SIEMENS 制造商全稱:Siemens Semiconductor Group 功能描述:Components for Entertainment Electronics |
| TUA6014-K | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Components for Entertainment Electronics |
| TUA6014-S | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Components for Entertainment Electronics |
| TUA6014XS | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Components for Entertainment Electronics |
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