參數(shù)資料
型號: TUA6024-2
廠商: INFINEON TECHNOLOGIES AG
元件分類: 調(diào)諧器
英文描述: 2-BAND, VIDEO TUNER, PDSO28
封裝: 1 MM HEIGHT, PLASTIC, TSSOP-28
文件頁數(shù): 9/40頁
文件大?。?/td> 693K
代理商: TUA6024-2
Functional Description
3 - 10
TUA6024-2
Wireless Components
Specification, July 2001
line to LOW (acknowledge condition). The first byte is comprised of seven
address bits. These are used by the processor to select the PLL from several
peripheral components (chip select). The LSB bit (R/W) determines whether
data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte.
If the address byte indicates a READ operation, the PLL generates an acknowl-
edge and then shifts out the status byte onto the SDA line. If the processor gen-
erates an acknowledge, a further status byte is output; otherwise the data line
is released to allow the processor to generate a stop condition. The status word
consists the lock flag and the power-on flag.
Four different chip addresses can be set by appropriate DC level at pin AS (see
While applying the supply voltage, a power-on reset circuit prevents the PLL
from setting the SDA line to LOW, which would block the bus. The power-on
reset flag POR is set at power-on and when VCC falls below 3.2 V. It will be reset
at the end of a READ operation.
相關PDF資料
PDF描述
TUA6024-K 2-BAND, VIDEO TUNER, PDSO28
TUA6024-S 2-BAND, VIDEO TUNER, PDSO28
TUA6026K 2-BAND, VIDEO TUNER, PDSO28
TUA6026S 2-BAND, VIDEO TUNER, PDSO28
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