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參數(shù)資料
| 型號： | TVP3703-170 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（雙鎖相環(huán)，先進(jìn)的視頻接口調(diào)色器） |
| 文件頁數(shù)： | 8/21頁 |
| 文件大小： | 427K |
| 代理商： | TVP3703-170 |
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
register content descriptions (continued)
POWER MANAGEMENT REGISTER A (Index 0007h)
BIT
FUNCTION
RESET
VALUE
SLEEP
MODE
7
Reserved (write 1)
1
1
6
Reserved (write 0)
0
1
5
1 = Power-down palette RAM
0
0
4
Reserved (write 0)
0
1
3
Reserved
1
1
2–0
Indicates the effect of selecting sleep mode (the power management
register is not modified).
Reserved (write 0)
0
1
POWER MANAGEMENT REGISTER B (Index 0008h)
BIT
FUNCTION
RESET
VALUE
7–3
Reserved
Not reset
2
1 = Power-down crystal oscillator
0
1
1 = Power-down VCLK generator
0
0
1 = Power-down MCLK generator
0
PLL PARAMETERS LOW REGISTERS
(Indexes 0020h, 0022h, . . . 0046h)
BIT
FUNCTION
RESET
VALUE
7
VCLK/MCLK source select 0 (see Table 4)
M value
See Table 3
6–0
PLL PARAMETERS HIGH REGISTERS
(Indexes 0021h, 0023h, . . . 0047h)
BIT
FUNCTION
RESET
VALUE
7
VCLK/MCLK source select 1 (see Table 4)
See Table 3
T bl 3
6–5
N2 value
4–0
N1 value
Table 4. VCLK/MCLK Source Select
(PLL parameters high and low registers – bit 7)
SOURCE
SELECT
1
SOURCE
SELECT
0
VCLK/MCLK FUNCTION
PLL
USED
0
0
fO
M
2
(
N1
2
)
2N2
f
I
XIN
Yes
0
1
Reserved
1
0
fO
fO = fI(XIN) direct
fI XIN
2N2
No
1
1
No
See power management features section.
CLOCK SYNTHESIZER CONTROL REGISTER
(Index 0048h)
BIT
FUNCTION
RESET
VALUE
7
Reserved
0
6
0 = Select VCLK by terminals VS0–VS3
1 = Select VCLK by bits 3–0
0
5–4
MCLK select (M0–M3)
0
3–0
VCLK select (V0–V15) if enabled by bit 6
0
CRC TEST REGISTER
(Index FFD6h)
BIT
VALUE
FUNCTION
RESET
VALUE
7–6
0 0
Blue selection
Not reset
0 1
Green selection
1 0
Red selection
1 1
None selected
5–3
0 0 0
1 1 1
Bit 0 selected
Bit 7 selected
Not reset
2
1
→
0
0
Transition initializes start of CRC
1
1
Use pixel bus input
1
Use self-test-generated patterns
0
0
Reserved
CRC LOW BYTE (Bits 7–0)
(Index FFD7h)
BIT
FUNCTION
VALUE
7–0
Low byte of CRC value
Not reset
CRC HIGH BYTE (Bits 15–8)
(Index FFD8h)
BIT
FUNCTION
RESET
VALUE
7–0
High byte of CRC value
Not reset
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