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參數(shù)資料
| 型號： | TVP5150APBSR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 14/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC NTSC/PAL/SECAM DECODER 32TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻解碼器 |
| 應(yīng)用： | 移動電話，PDA，播放器 |
| 電壓 - 電源，模擬： | 1.8V |
| 電壓 - 電源，數(shù)字： | 1.8V，3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（5x5） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 887 (CN2011-ZH PDF) |
| 配用： | TVP5150AEVM-ND - TVP5150AEVM 296-23058-ND - EVAL MODULE FOR DM642 TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| 其它名稱： | 296-16846-6 |
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2.15.2.2 Read Phase 2
Step 7
0
I2C Start (master)
S
Step 8
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
0
X
1
Step 9
9
I2C Acknowledge (slave)
A
Step 10
7
6
5
4
3
2
1
0
I2C Read data (slave)
Data
Step 11
9
I2C Not acknowledge (master)
A
Step 12
0
I2C Stop (master)
P
Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
2.15.2.3 I2C Timing Requirements
The TVP5150A decoder requires delays in the I2C accesses to accommodate its internal processor’s timing. In
accordance with I2C specifications, the TVP5150A decoder holds the I2C clock line (SCL) low to indicate the wait
period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the
maximum delays must always be inserted where required. These delays are of variable length; maximum delays are
indicated in the following diagram:
Normal register writing address 00h8Fh (addresses 90hFFh do not require delays)
Start
Slave address
(B8h)
Ack
Subaddress
Ack
Data
(XXh)
Ack
Wait 64
s
Stop
2.16 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive the PLL.
This may be input to the TVP5150A decoder on terminal 5 (XTAL1), or a crystal of 14.31818-MHz fundamental
resonant frequency may be connected across terminals 5 and 6 (XTAL2). Figure 25 shows the reference clock
configurations. For the example crystal circuit shown (a parallel-resonant crystal with 14.31818-MHz fundamental
frequency), the external capacitors must have the following relationship:
CL1 = CL2 = 2CL CSTRAY,
where CSTRAY is the terminal capacitance with respect to ground. Figure 25 shows the reference clock
configurations.
TVP5150A
5
XTAL1
14.31818-MHz
Crystal
6
XTAL2
TVP5150A
5
XTAL1
6
XTAL2
CL1
CL2
14.31818-MHz
TTL Clock
Figure 25. Reference Clock Configurations
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP5150APBSRG4 | 功能描述:視頻 IC Ultralo Pwr NTSC/PAL SECAM Video Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5150PBS | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 VERY LOW POWER VIDEO DECODER RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| TVP5150PBS | 制造商:Texas Instruments 功能描述:IC DECODER VIDEO SMD |
| TVP5150PBSG4 | 功能描述:視頻 IC VERY LOW POWER VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5150PBSR | 功能描述:視頻 IC Very Low Power Video Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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