參數(shù)資料
型號: TWL1110PBSR
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP32
封裝: PLASTIC, QFP-32
文件頁數(shù): 20/40頁
文件大?。?/td> 564K
代理商: TWL1110PBSR
TWL1110
VOICE-BAND AUDIO PROCESSOR (VBAP
)
SLWS103 – NOVEMBER 2000
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
I2C- bus protocols (continued)
Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data
bytes, transferred between the start and stop conditions, is determined by the master device (microprocessor).
When addressed, the VBAP generates an acknowledge after the reception of each byte. The master device
must generate an extra clock pulse that is associated with this acknowledge bit.
The VBAP must pull down the SDA line during the acknowledge clock pulse so that the SDA line is at stable
low state during the high period of the acknowledge related clock pulse. Setup and hold times must be taken
into account. During read operations, the master device must signal an end of data to the slave by not generating
an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave (VBAP) must leave
the data line high to enable the master device to generate the stop condition.
clock frequencies and sample rates
A fixed PCMSYN rate of 8 kHz determines the sampling rate.
register map addressing
REG
BITS
REG
07
06
05
04
03
02
01
00
Power control
00
Sidetone En
TXEn
RX TX En
MICSEL
BIASEn
RXEn
EAROUT
Sel
PWRUP
Mode control
01
Comp Sel
TMEn
PCMLB
Comp En
BUZZEn
RXFLTR
En
TXFLTR
En
TXSLOPE
En
TXPGA
02
X
TP3
TP2
TP1
TP0
ST2
ST1
ST0
RXPGA
03
RP3
RP2
RP1
RP0
RV3
RV2
RV1
RV0
High DTMF
04
HIFREQ
Sel7
HIFREQ
Sel6
HIFREQ
Sel5
HIFREQ
Sel4
HIFREQ
Sel3
HIFREQ
Sel2
HIFREQ
Sel1
HIFREQ
Sel0
Low DTMF
05
LOFREQ
Sel7
LOFREQ
Sel6
LOFREQ
Sel5
LOFREQ
Sel4
LOFREQ
Sel3
LOFREQ
Sel2
LOFREQ
Sel1
LOFREQ
Sel0
AUX
06
MCLK
Detect
RXPGA2
DTMFH1
DTMFH0
DTML1
DTMFL0
AMVX
MCLK sel
For voice mode only
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