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參數(shù)資料
| 型號： | TWO-CHIP |
| 英文描述： | High voltage fast-switching NPN power transistor |
| 中文描述： | 雙芯片的移動處理器（117k解決方案） |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 117K |
| 代理商： | TWO-CHIP |
AN99-12
TWO CHIP SOLUTION FOR
MOBILE CPUs
2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
January 5, 2000
8
FUNCTIONAL DESCRIPTION
SUPPLY
The chip is optimized to operate from a 3.3V + 5% rail
but is also designed to work up to 6V maximum supply
voltage. If V
CC
is out of the 3.3V + 5% voltage range,
the quiescent current will increase somewhat and slight
degradation of line regulation is expected.
UNDER VOLTAGE LOCK-OUT CIRCUIT
The under voltage lockout circuit consists of two com-
parators, the low battery and low V
(low supply volt-
age) comparators. The output of the comparator gated
with the Enable signal turns on or off the internal bias,
enables or disables the CO output, and initiates or
resets the soft start timers.
POWER GOOD GENERATOR
If the chip is enabled but not in UVLO condition, and
the core voltage gets within +10% of the VID pro-
grammed value, then a high level Power Good signal is
generated on the PWRGD pin to trigger the CPU
power up sequence. If the chip is either disabled or en-
abled in UVLO condition, then PWRGD stays low.
This condition is satisfied by the presence of an inter-
nal 200k
pull-down resistor connected from PWRGD
to ground.
During soft start, PWRGD stays low independently
from the status of Vcore voltage. During this time,
PWRGD status is “don’t care”.
BAND GAP REFERENCE
A better than +1% precision band gap reference acts
as the internal reference voltage standard of the chip,
which all critical biasing voltages and currents are de-
rived from. All references to VREF in the equations to
follow will assume V
REF
= 1.7V.
CORE CONVERTER CONTROLLER
Precision VID DAC Reference
The 5-bit digital to analog converter (DAC) serves as
the programmable reference source of the core com-
parator. Programming is accomplished by CMOS logic
level VID code applied to the DAC inputs. The VID
code vs. the DAC output is shown in the Output Volt-
age Table. The accuracy of the VID DAC is main-
tained on the same level as the band gap reference.
There is a 10μA pull-up current on each DAC input
while EN is high.
Core Comparator
This is an ultra-fast hysteretic comparator with a typical
propagation delay of approximately 20ns at a 20mV
overdrive. Its hysteresis is determined by the resis-
tance ratio of two external resistors, R
and R
OH
, and
the high accuracy internal reference voltage, V
REF
.
This chip can be used in standard hysteretic mode
controller configuration and in DSPS (Dynamic Set
Point Switching) hysteretic controller scheme.
In standard hysteretic controller configuration
, the
core comparator compares the output voltage of the
core converter, V
CORE
to the VID code programmed
DAC voltage, V
DAC
V
CORE
(t) = V
DAC
+ V
HYST
(t)
The core voltage ramps up and down between the two
thresholds determined by the hysteresis of the com-
parator:
V
HCORE
= V
DAC
+ V
HYST
V
LCORE
= V
DAC
-
V
HYST
In DSPS hysteretic controller configuration
, the
core comparator compares the core voltage, V
CORE
, not
to the DAC voltage, V
DAC
directly but rather to a voltage
less than the DAC voltage by a DSPS voltage, V
DSPS
.
V
CORE
(t) = V
DAC
-
V
DSPS
(t) + V
HYST
(t)
The DSPS voltage is a function of the load current. It is
generated from the current sense voltage, V
,
de-
veloped across a sense resistor, R
which is inserted
in series with the main buck inductor and also used for
current sensing for the cycle-by-cycle current limiting.
The sense voltage is scaled up by the DSPS gain, A
D-
, which is set by the resistance ratio of two external
resistors, R
DAC
and R
CORE
.
REF
HYS
OH
HYS
V
R
R
V
=
)
i
R
)
R
R
1
)
V
A
)
V
CORE
CS
CORE
DAC
CS
DSPS
DSPS
+
=
=
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