參數(shù)資料
型號： TWR-MECH
廠商： Freescale Semiconductor
文件頁數(shù)： 46/46頁
文件大?。?/td> 0K
描述： KIT TOWER ROBOT SENSOR MOTOR
視頻文件： Freescale Tower Overview - Another Geek Moment
Freescale Tower Labs 1 & 2 - Another Geek Moment
設(shè)計資源： Tower Mechanical Drawing
標(biāo)準(zhǔn)包裝： 1
系列： ColdFire®
主要目的： 機(jī)器人
嵌入式： 是，MCU，32 位
已用 IC / 零件： MCF52259，MMA8451Q，MPR121
主要屬性： 32 位 MCU，3 軸加速傳感器，接觸式傳感器
已供物品： 板
MCF52259 ColdFire Microcontroller, Rev. 5
Family Configurations
Freescale
9
1.2.2
V2 Core Overview
The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage
instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is
a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP).
The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage
(AGEX) performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire instruction set architecture revision A+ with support for a separate user stack pointer
register and four new instructions to assist in bit processing. Additionally, the core includes the enhanced multiply-accumulate
(EMAC) unit for improved signal processing capabilities. The EMAC implements a three-stage arithmetic pipeline, optimized
for 32x32 bit operations, with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and
unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The EMAC
provides support for execution of DSP operations within the context of a single processor at a minimal hardware cost.
1.2.3
Integrated Debug Module
The ColdFire processor core debug interface is provided to support system debugging with low-cost debug and emulator
development tools. Through a standard debug interface, access to debug information and real-time tracing capability is provided
on 144-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit
emulators.
The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register,
a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the
dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint
registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or
dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.
This device implements revision B+ of the ColdFire Debug Architecture.
The processor’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be
serviced while processing a debug interrupt event. This ensures the system continues to operate even during debugging.
To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports.
These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining
processor activity at the CPU’s clock rate. The device includes a new debug signal, ALLPST. This signal is the logical AND of
the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).
The full debug/trace interface is available only on the 144-pin packages. However, every product features the dedicated debug
serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
1.2.4
JTAG
The processor supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action
Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and
three test registers (a 1-bit bypass register, a boundary-scan register, and a 32-bit ID register). The boundary scan register links
the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system
logic.
The device implementation can:
Perform boundary-scan operations to test circuit board electrical continuity
Sample system pins during operation and transparently shift out the result in the boundary scan register
Bypass the device for a given circuit board test by effectively reducing the boundary-scan register to a single bit
Disable the output drive to pins during circuit-board testing
Drive output pins to stable levels
相關(guān)PDF資料
PDF描述
NRS6012T100MMGJ INDUCTOR POWER 10UH 1.2A SMD
REC5-243.3DRWZ/H4/C CONV DC/DC 5W 9-36VIN +/-3.3V
UPJ1C101MED1TD CAP ALUM 100UF 16V 20% RADIAL
342A012-12-0 BOOT MOLDED
REC5-243.3DRWZ/H4/A CONV DC/DC 5W 9-36VIN +/-3.3V
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TWR-MEM 功能描述:存儲器 IC 開發(fā)工具 Memory Module for Tower RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Reference Boards 工具用于評估:M24LR64-R 存儲容量:64 kbit 存儲類型:EEPROM 工作電源電壓:1.8 V to 5.5 V
TWR-MEM 制造商:Freescale Semiconductor 功能描述:TOWER SYSTEM - MEMORY CONTROLL
TWR-MEM-PISMO 功能描述:存儲器 IC 開發(fā)工具 Tower Memory Pismo RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Reference Boards 工具用于評估:M24LR64-R 存儲容量:64 kbit 存儲類型:EEPROM 工作電源電壓:1.8 V to 5.5 V
TWR-METRO-KIT-EU 功能描述:WiFi/802.11開發(fā)工具 TWR-METRO-KIT FOR EU RoHS:否 制造商:Roving Networks 產(chǎn)品:Evaluation Boards 工具用于評估:RN-171 支持協(xié)議:802.11 b/g 頻率:2.4 GHz 接口類型:UART 工作電源電壓:2 V to 16 V
TWR-METRO-KIT-JA 功能描述:WiFi/802.11開發(fā)工具 TWR-METRO-KIT FOR JA RoHS:否 制造商:Roving Networks 產(chǎn)品:Evaluation Boards 工具用于評估:RN-171 支持協(xié)議:802.11 b/g 頻率:2.4 GHz 接口類型:UART 工作電源電壓:2 V to 16 V
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