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參數(shù)資料
| 型號： | TZA1031HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 6/52頁 |
| 文件大?。?/td> | 207K |
| 代理商： | TZA1031HL |
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2002 Jun 06
14
Philips Semiconductors
Product specication
Signal processing IC for DVD rewriteable
TZA1031
The actual laser power signal produced by the laser driver
has a delay (10 + D2)T with respect to EFMDP and
EFMDN (see Fig.5). In the device this actual power signal
is represented by LIGHT, which therefore is delayed
(10+D2)T of EFMCP and EFMCN with respect to EFMDP
and EFMDN. The signal RS, used for sampling the
RF signal to obtain the disc’s ‘reflection’, is synchronously
derived from LIGHT. It is either active or inactive, defined
by bit ENRS and the state of r/w. When it is inactive
(ENRS = 0 or r/w = 1) RS is always HIGH. When it is
active (ENRS = 1 and r/w = 0) RS goes HIGH after m1
periods T/2 after the trailing edge of LIGHT (i.e. in the
‘land’ region) and LOW after (n1 2) periods T/2 after the
rising edge of LIGHT with m1 = 0 to 7 and n1 = 0 to 7. The
duty cycle of EFMCP and EFMCN can be assumed to be
50%.
The signals AINTON and ASTROBE are derived from
LIGHTA (‘a(chǎn)dvanced light’) which is delayed (9 + D2) EFM
clocks T with respect to EFMCP and EFMCN. AINTON
and ASTROBE are either (together) active or inactive,
defined by bit ENALF. When they are inactive
(ENALF = 0) both AINTON and ASTROBE are LOW.
When they are active (ENALF = 1) AINTON goes HIGH
after m2 periods T/2 after the rising edge of LIGHTA (i.e. in
the ‘pit’ region) and ASTROBE goes HIGH after (n2 +1)
periods T/2 after the rising edge of LIGHTA. The pulse
duration of ASTROBE is always T, and a period T/2 later
AINTON also goes LOW. This implies that the pulse
duration of AINTON equals (n2 m2 + 4) periods T/2.
7.1.2
EFMTIM INPUT INTERFACE
To minimize crosstalk by the high frequency signals
EFM clock and EFM data, the inputs for these signals are
made balanced current mode inputs. The inputs
EFMDP, EFMDN, EFMCP and EFMCN show a resistance
of about 100
to GND. A logic HIGH-level is received if
IEFMDP >IEFMDN or IEFMCP >IEFMCN. If IEFMDP <IEFMDN or
IEFMCP <IEFMCN a logic LOW-level is received. The
interface is intended to be driven from standard
complementary CMOS outputs with a resistor in series.
For instance EFMDP is connected to EFMdata and
EFMDN is connected to EFMdata, both with a series
resistor. To achieve sufficient speed, the current
corresponding to a HIGH-level should be large enough,
and therefore the resistors should not be too large. For
applications up to 16
× CD or 4 × DVD write a high level
current of 330
A is sufficient, corresponding to a 10 k
series resistance for 3.3 V supply.
7.1.3
EFMTIM TEST OUTPUT
An output test signal TIMOUT is defined for the EFMTIM
block. It can be used to check the timing relation between
the ingoing EFM signal and one of the output signals
AINTON, ASTROBE, RS and r/w. The selection of the
output signal is done by the 3-bit register TIM6, where the
MSB is used to enable or disable TIMOUT.
Remark: the voltage swing on TIMOUT is from 0 V to VDD,
so direct interfacing to digital circuitry on a 3.3 V supply is
not generally possible.
7.1.4
EFMTIM RESET
The EFMTIM block has a local reset input which is
software-controlled by bit RST of the serial input register.
By sending the sequence 0
→ 1 → 0 to bit RST the
asynchronous reset circuit in EFMTIM is loaded and the
actual reset is established after a number of edges (<16)
on EFMCP and EFMCN.
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