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參數(shù)資料
| 型號(hào)： | ST72344S2T6TR |
| 廠(chǎng)商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, ROHS COMPLIANT, TQFP-32 |
| 文件頁(yè)數(shù)： | 47/246頁(yè) |
| 文件大?。?/td> | 2016K |
| 代理商： | ST72344S2T6TR |
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On-chip peripherals
ST72344xx, ST72345xx
140/246
SCI clock tolerance
During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th
samples is considered as the bit value. For a valid bit detection, all the three samples should
have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and
10th samples are 0, 1 and 1 respectively, then the bit value is “1”, but the Noise Flag bit is
set because the three samples values are not the same.
Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples
have the desired bit value. This means the clock frequency should not vary more than 6/16
(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when
receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed
3.75%.
Note:
The internal sampling clock of the microcontroller samples the pin value on every falling
edge. Therefore, the internal sampling clock and the time the application expects the
sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit
length is 64 s), then the 8th, 9th and 10th samples will be at 28 s, 32 s and 36 s
respectively (the first sample starting ideally at 0 s). But if the falling edge of the internal
clock occurs just before the pin value changes, the samples would then be out of sync by
~4 s. This means the entire bit length must be at least 40 s (36 s for the 10th sample
+ 4 s for synchronization with the internal sampling clock).
Clock deviation causes
The causes which contribute to the total deviation are:
●
DTRA: Deviation due to transmitter error (Local oscillator error of the transmitter or the
transmitter is transmitting at a different baud rate).
●
DQUANT: Error due to the baud rate quantization of the receiver.
●
DREC: Deviation of the local oscillator of the receiver: This deviation can occur during
the reception of one complete SCI message assuming that the deviation has been
compensated at the beginning of the message.
●
DTCL: Deviation due to the transmission line (generally due to the transceivers)
All the deviations of the system should be added and compared to the SCI clock tolerance:
DTRA + DQUANT + DREC + DTCL < 3.75 %
Noise error causes
See also description of noise error in Receiver.
●
Start bit: the noise flag (NF) is set during start bit reception if one of the following
conditions occurs:
–
A valid falling edge is not detected. A falling edge is considered to be valid if the
three consecutive samples before the falling edge occurs are detected as '1' and,
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST72344S4T6 | MICROCONTROLLER, PQFP44 |
| ST72345C4T6TR | MICROCONTROLLER, PQFP48 |
| ST72521AR7T1/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| ST72521R7T5/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| ST72521AR7TC/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72345 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8-BIT MCU WITH UP TO 16K FLASH MEMORY, 10-BIT ADC, TWO 16-BIT TIMERS, TWO I2C, SPI, SCI |
| ST72345-D/RAIS | 功能描述:子卡和OEM板 8 BITS MICROCONTR RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| ST72361 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8-bit MCU with Flash or ROM, 10-bit ADC, 5 timers, SPI, 2x LINSCI⑩ |
| ST72361_07 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8-bit MCU with Flash or ROM, 10-bit ADC, 5 timers, SPI, 2x LINSCI⑩ |
| ST72361K6T6 | 制造商:STMicroelectronics 功能描述:ROMLESS MICRO WITH 2 UART - Bulk |
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