參數(shù)資料
型號(hào)： U3900BM-AFN
英文描述： Programmable Telephone Audio Processor
中文描述： 程控電話音頻處理器
文件頁(yè)數(shù)： 5/34頁(yè)
文件大?。?/td> 762K
代理商： U3900BM-AFN
U3900BM
Target Specification
Rev. A2, 25-Aug-98
13 (34)
4.1
Ringing Frequency Detector
(RFD)
The U3900BM provides an output signal for the
microcontroller. This output signal is always double the
value of the input signal (ringing frequency). It is
generated by a current comparator with hysteresis. The
levels for the on-threshold are programmable in 16 steps
and the off-level is fixed. Every change of the comparator
output generates a high level at the interrupt output INT.
The information can then be read out by means of a serial
bus with either a normal or a fast read mode. The block
RFD is always enabled.
RINGTH[0:3]
VRING
min. 0
7 V
max. 15
22 V
step
1 V
5
Clock Output Divider
Adjustment
The Pin OSCOUT is a clock output which is derived from
the crystal oscillator of the ceramic resonator. It can be
used to drive a microcontroller or another remote
component and thereby reduces the number of crystals
required. The oscillator frequency can be divided by 1, 8,
16, 32. During power-on reset, the divider will be reset to
1 until it is changed by setting the serial bus.
CLK[0:1]
Divider
Frequency
0
1
3.58 MHz
1
8
447 kHz
2
16
224 kHz
3
32
112 kHz
6
Serial Bus Interface
The circuit is controlled by an external microcontroller
through the serial bus. The serial bus is a bi-directional
system consisting of a one-directional clock line (BCL)
which is always driven by the microcontroller, and a
bi-directional data-signal line. It is driven by the
microcontroller as well as from the U3900BM (see
figure 12). The serial bus requires external pull-up
resistors as only open-collector transistors (Pin BDA) are
integrated.
WRITE:
The data is a 12-bit word:
A0 – A3: address of the destination register (0 to 15)
D0 – D7: content of the register
The data line must be stable when the clock is high. Data
must be shifted serially.
After 12 clock periods, the write indication is sent. Then,
the transfer to the destination register is (internally)
generated by a strobe signal transition of the data line
when the clock is high (see figure 13).
READ:
There is a normal and a fast-read cycle.
In the normal read cycle, the microcontroller sends a 4-bit
address followed by the read indicator, then an 8-bit word
is read out. The U3900BM drives the data line (see
figure 14).
The fast read cycle is indicated by a strobe signal. With
the following two clocks the U3900BM reads out the sta-
tus bits RFDO and LIDET which indicate that a ringing
signal or a line signal is present (see figure 15).
6.1
Bus Timing
twSTA
thSTA
tL
tr
BDA
BCL
thDAT
thSTA
tf
tH
tsSTA
tsSTOP
14793
thDAT
Sf
Sr
Sf = Strobe falling, SR = Strobe rising
Sf
Figure 13. Bus timing
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