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參數(shù)資料
| 型號： | U3900BM-AFNG3 |
| 英文描述： | Programmable Telephone Audio Processor |
| 中文描述： | 程控電話音頻處理器 |
| 文件頁數(shù)： | 14/34頁 |
| 文件大?。?/td> | 762K |
| 代理商： | U3900BM-AFNG3 |
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U3900BM
Target Specification
Rev. A2, 25-Aug-98
21 (34)
14614
–
+
I
AFS
BUS
TXA
SAI
I
GSA
BUS
INLDT
TX
INLDR
TX
TLDR
TLDT
Figure 22. System configuration for group listening
11 Analog-to-Digital Converter (ADC)
The circuit is a 7-bit successive approximation analog-
to-digital converter in switched capacitor technique. An
internal bandgap circuit generates a 1.25-V reference
voltage
which
is
the
equivalent
of
1
MSB.
1 LSB = 19.5 mV. The possible input voltage at ADIN is
0 to 2.48 V.
The ADC needs an SOC (Start Of Conversion) signal. In
the ‘High’ phase of the SOC signal, the ADC is reset.
50
ms after the beginning of the ‘Low’ phase of the SOC
signal the ADC generates an EOC (End Of Conversion)
signal which indicates that the conversion is finished. The
rising edge of EOC generates an interrupt at the INT
output. The result can be read out by the serial bus.
Voltages higher than 2.48 V have to be divided. The
signal which is connected to the ADC is determined by
5 bits
ADC0,
ADC1,
ADC2,
ADC3
and
NWT.
TLDR/TLDT measuring is possible relative to a preced-
ing reference measurement. The current range of IL can
be doubled by ADCR. If ADCR is ‘High’, S has the value
0.5, otherwise S = 1.
The source impedance at ADIN must be lower than
250 k
W.
Accuracy: 1 LSB
± 3%
14594
SOC
50
s
EOC
Figure 23. Timing of ADC
14595
ADIN
0.4
VB
0.4
VMPS
0.4
SAO1
0.75
VMP
8
(TLDR–REF)
8
(TLDT–REF)
0.4
OFF1
0.4
OFF2
0.4
OFF3
IL
20mV/(1mA
S)
ADC
MSB
BIT5
BIT4
BIT3
BIT2
BIT1
LSB
SOC
EOC
Figure 24. ADC input selection
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