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DESCRIPTION (CONTINUED)
DISSIPATION RATINGS
UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
SLUS365A – APRIL 1999 – REVISED AUGUST 2005
The UC3827 can be set up in traditional voltage mode control using input voltage feedforward technique or in
current mode control. Using current mode control prevents potential core saturation of the push-pull transformer
due to mismatches in timing and in component tolerances. With average current mode control, precise control of
the inductor current feeding the push-pull stage is possible without the noise sensitivity associated with peak
current mode control. The UC3827 average current mode loop can also be connected in parallel with the voltage
regulation loop to assist only in fault conditions.
Other valuable features of the UC3827 include bidirectional synchronization capability, user programmable
overlap time (UC3827-1), user programmable gap time (UC3827-2), a high bandwidth differential current sense
amplifier, and soft start circuitry.
ORDERING INFORMATION(1)
PACKAGES
TA = TJ
PUSH-PULL TOPOLOGY
SOIC-24
PDIP-24
PLCC-28
Current Fed
UC1827J-1
-55°C to 125°C
Voltage Fed
UC1827J-2
Current Fed
UC2827DW-1
UC2827N-1
-
-40°C to 85°C
Voltage Fed
UC2827DW-2
UC2827N-2
-
Current Fed
UC3827DW-1
UC3827N-1
UC3827Q-1
0°C to 70°C
Voltage Fed
UC3827DW-2
UC3827N-2
-
(1)
The DW and Q packages are also available taped and reeled. Add a TR suffix to the device type (i.e., UC2827DWTR-1).
PACKAGE
(
θ
JA) JUNCTION-TO-AMBIENT
(
θ
JC) JUNCTION-TO-WHAT?
TEMPERATURE (°C/W)
24-pin (N)
60(1)
30
24-pin (J)
70 to 90
28(2)
28-pin (DW)
71 to 83(3)
24(3)
28-pin (QLCC)
40-65(1)
30
(1)
Specified
θ
JA (junction-to-ambient) refers to devices mounted to 5-in
2 FR4 PC board with 1 oz. copper where noted. When a resistance
range is given, the lower values refer to a 5-in2 aluminum PC board. The test PWB is 0.062 inches thick and typically used 0.635 mm
trace widths for power packages and 1.3 mm trace widths for non-power packages with a 100 × 100 mil probe land area at the end of
each trace.
(2)
Specified
θ
JC (junction-to-what?) data values stated were derived from MIL-STD-1835B which states "The baseline values shown are
worst case (mean + 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 mils2. For
device sizes greater than 14400 mils2 use the following values; dual-in-line, 11 °C/W; flat pack, 10 °C/W; pin grid array, 10 °C/W pin grid
array, 10 °C/W."
(3)
Modeled data. If there is a value range given for
θ
JA, the lower value refers to a 3 x 3 in., 1-oz, internal copper ground plane. The higher
value refers to a 1 x 1 in. ground plane. All model data assumes only one trace for each non-fused lead.
2