參數(shù)資料
型號: UC3852DTR
英文描述: Low voltage CMOS octal D-type latch with 3 state outputs non inverting
中文描述: 功率因數(shù)控制器
文件頁數(shù): 12/13頁
文件大?。?/td> 265K
代理商: UC3852DTR
MECHANICAL DATA
MSOT008B – JANUARY 1995 – REVISED SEPTEMBER 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
KC (R-PSFM-T5)
PLASTIC FLANGE-MOUNT
4040208/E 09/00
0.420 (10,67)
0.380 (9,65)
0.185 (4,70)
0.175 (4,46)
0.055 (1,40)
0.045 (1,14)
0.147 (3,73)
0.137 (3,48)
0.340 (8,64)
0.330 (8,38)
1.037 (26,34)
0.997 (25,32)
0.040 (1,02)
0.030 (0,76)
0.113 (2,87)
0.103 (2,62)
0.122 (3,10)
0.102 (2,59)
0.025 (0,64)
0.012 (0,30)
0.146 (3,71)
0.156 (3,96)
DIA
(see Note C)
0.125 (3,18)
0.067 (1,70)
0.268 (6,81)
5
1
M
0.010 (0,25)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Lead dimensions are not controlled within this area.
D. All lead dimensions apply before solder dip.
E. The center lead is in electrical contact with the mounting tab.
相關PDF資料
PDF描述
UC3852J Octal D-type flip flop with 3 state outputs non inverting
UC3852N Dual D-type flip flop with preset and clear
UC3853D Quad exclusive OR gate
UC3853DTR Low voltage CMOS quad 2-input NAND gate with 5V tolerant inputs
UC3853J Low voltage CMOS quad 2-input NOR gate with 5V tolerant inputs
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