參數(shù)資料
型號(hào)： UCC28517N
廠(chǎng)商： Texas Instruments, Inc.
元件分類(lèi)： 基準(zhǔn)電壓源/電流源
英文描述： ADVANCED PFC/PWM COMBINATION CONTROLLERS
中文描述： 先進(jìn)PFC / PWM組合控制器
文件頁(yè)數(shù)： 16/39頁(yè)
文件大小： 725K
代理商： UCC28517N
SLUS517B DECEMBER 2002 REVISED AUGUST 2004
16
www.ti.com
APPLICATION INFORMATION
power stage elements
The power stage elements include the following elements: C13, D15, L1, R2, R5, Q1, Q2, T1. Details
concerning the PWM stage elements C2, D4, D5, Q2 and T1 will not be discussed in detail here, due to their
dependence on the choice PWM stage topology. The PWM stage is an isolated dc-to-dc topology with the same
stresses and loss mechanisms that are typical for the selected topology. An estimation of the average steady
state duty ratio of the PWM stage and the Q2 switch current will be needed for stress estimations in the PFC
stage. Also, the natural step response of the PWM stage is required to estimate the soft start capacitor, C5, and
the bias supply capacitor, C3.
The selection process of the PFC stage elements C1, C3, D13 and Q1 are discussed in detail here. In general,
the selection process for the PFC stage elements is the same as for a typical fixed switching frequency PFC
design, except for capacitor C1 due to PFC/PWM stage synchronization.
Diode bridge D1 is selected to withstand the rms line current and the peak ac line voltage. Diode D2 allows
capacitor C1 to charge during initial power up without saturating L1 and it is selected to withstand the peak inrush
current and peak of the maximum ac line voltage. Additional inrush current limiting circuitry in series with the
ac line could be required, depending on agencies or situations.
The PFC stage inductor, L1, is selected to have a maximum current ripple at the minimum ac line voltage.
Typically a ripple factor, k
RF
, is chosen to be about 0.2. If the line current has excessive crossover distortion,
a larger ripple factor (perhaps 0.3) will reduce the distortion but the line current will have more switching ripple.
Initially, the inductance can be estimated by approximating the input power equal to the output power.
L1
V
AC(min)
2
D
1(min)
k
RF
T
S(pfc)
P
IN
where, k
RF
i
L1(pp)
i
L1(max)
and T
s(pfc)
is
1
switching frequency of the PFC
Inductor L1 must be designed to withstand the maximum ac rms line current without saturation at the peak ac
line current.
Select power MOSFET Q1 and diode D3 with the same criteria that is normally used for fixed switching
frequency PFC design. They must have sufficient voltage rating to withstand the energy storage voltage, V
C1
and they must have sufficient current ratings. Gate drive resistor R9 is necessary to limit the source and sink
current from the GT1 pin. Some circumstances require additional gate drive components for improved
protection and performance.
[10]
A similar gate drive resistor, R10, is required between the GT2 pin and the gate
of Q2 for the same reason.
(5)
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