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參數(shù)資料
| 型號(hào)： | UCC2882 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Average Current Mode Synchronous Controller With 5-Bit DAC |
| 中文描述： | 平均電流模式同步控制器，5位DAC |
| 文件頁(yè)數(shù)： | 5/14頁(yè) |
| 文件大?。?/td> | 579K |
| 代理商： | UCC2882 |
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5
UCC2882/-1
UCC3882/-1
GATELO:
This output provides a low impedance totem
pole driver to drive the low-side synchronous external
MOSFET. A series resistor between this pin and the gate
of the external MOSFET is recommended to prevent gate
drive ringing and overshoot. Good layout techniques
should be used to prevent GATELO from ringing more
than 0.3V below PGND. The VDRVLO pin provides the
power for GATELO. GATELO is disabled during UVLO
conditions. For the 2882/3882 only, GATELO is also dis-
abled when the COMMAND voltage is programmed be-
tween 1.3 and 1.75V, or where the D0-D4 pins are all
logic high levels, indicating no processor present.
GND:
Ground reference for the device. All voltages, with
the exception of the GATE voltages, are measured with
respect to GND. Bypass capacitors on VIN, VREF, VSNS
and COMMAND should be connected directly to the
ground plane near GND.
IS-:
This pin is the inverting input to the current sense
amplifier and is connected to the low side of the average
current sense resistor.
IS+:
This pin is the non-inverting input to the current
sense amplifier and is connected to the high side of the
average current sense resistor.
ISOUT:
This pin is the output of the current sense ampli-
fier. The voltage on this pin is equal to the voltage across
the sense resistor multiplied by 16 and biased up by the
COMMAND voltage. This voltage is used for Average
Current mode control and for current limiting.
PGND:
This pin provides a dedicated ground for the out-
put gate drivers. The GND and PGND pins should be
connected externally using a short PC board trace or
plane. Decouple VDRVHI and VDRVLO to PGND with
low ESR capacitor of at least 0.1
μ
F.
PWRGD:
This pin is an open drain output which is driven
low to reset the microprocessor when VSNS rises above
or falls below its nominal value by 9%. The on resistance
of the open-drain switch will be no higher than 470
.
This output should be pulled up to a logic level voltage
and should be programmed to sink 1mA or less.
RT:
This pin is used with CT to program the internal
PWM oscillator frequency. It is also used to program the
delay times between the external MOSFET turn on and
turn off periods, which eliminates cross conduction in
those MOSFETs. See the Applications Section for pro-
gramming the oscillator and for controlling cross conduc-
tion.
VDRVHI:
This pin supplies power to the high side output
driver, GATEHI. Connect VDRVHI to an 18V or lower
source for power supplies converting 12VDC to lower
voltages, and to a 12V source for systems for power sup-
plies converting 5VDC. This pin should be bypassed di-
rectly to PGND using a low ESR capacitor.
VDRVLO:
This pin supplies power to the low side output
driver, GATELO. VDRVLO is typically connected to a 12V
source, but may be connected to a 5V source for driving
logic level MOSFETs. This pin should be bypassed di-
rectly to PGND using a low ESR capacitor.
VIN:
This pin supplies power to the chip. Connect VIN to
a stable voltage source that is at least 10.8V above GND.
The GATEHI, GATELO and PWRGD outputs will be held
low until VCC exceeds the upper undervoltage lockout
threshold. This pin should be bypassed directly to GND.
VFB:
This pin is the inverting input to the error amplifier.
This input is connected to COMP through a feedback
network and to the power supply output through a resis-
tor or a divider network.
VREF:
This pin provides an accurate 5V reference and is
internally short circuit current limited. VREF powers the
D/A Converter and also provides a threshold voltage for
the UVLO comparator. For best reference stability, by-
pass VREF directly to GND with a low ESR, low ESL ca-
pacitor of at least 0.01
μ
F.
VSNS:
This pin is connected to the system output volt-
age through a low pass R-C filter. When the voltage on
VSNS rises above or falls below the COMMAND voltage
by 9%, the PWRGD output is driven low to reset the mi-
croprocessor. When the voltage on VSNS rises above
the COMMAND voltage by 17.5%, the OVP comparator
disables the GATEHI output and enables the GATELO
output, forcing 0% duty cycle on the power supply. This
pin is also used by the foldback current limiting circuitry
to indicate when the output voltage has been short cir-
cuited. VSNS should be decoupled very closely to the IC
with a capacitor to GND. The OV and UV comparators’
hysteresis is typically 20mV, requiring good layout and fil-
tering techniques to insure that noise and ground-bounce
do not inadvertently trip the OV and UV comparators. It is
recommended that an R-C filter set to approximately
Fs/10 be used to filter noise from the system output,
where Fs is the oscillator frequency.
PIN DESCRIPTIONS (continued)
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