參數(shù)資料
型號(hào)： UCC3882N-1
英文描述： 5-pin supervisor with watchdog timer and push-button reset
中文描述： 電流模式開(kāi)關(guān)電源控制器
文件頁(yè)數(shù)： 3/19頁(yè)
文件大?。?/td> 296K
代理商： UCC3882N-1
SLUS458C AUGUST 2001 REVISED SEPTEMBER 2003
3
www.ti.com
electrical characteristics V
DD
= 15 V (See Note 1), R
T
= 10 k
, C
T
= 3.3 nF, C
VDD
= 0.1
μ
F and no load
on the outputs, T
A
= 40
°
C to 105
°
C for the UCC28C4x and T
A
= 0
°
C to 70
°
C for the UCC38C4x,
T
A
= T
J
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Reference Section
Output voltage, initial accuracy
TA = 25
°
C
VDD = 12 V to 18 V
1mA to 20mA
IOUT = 1mA
4.9
5.0
5.1
V
Line regulation
0.2
20
mV
Load regulation
3
25
mV
mV/
°
C
V
μ
V
mV
Temperature stability
See Note 2
0.2
0.4
Total output variation
See Note 2
4.82
5.18
Output noise voltage
10 Hz to 10 kHz,
TA = 25
°
C,
TA = 125
°
C,
See Note 2
50
Long term stability
1000 hours,
See Note 2
5
25
Output short circuit
–30
–45
–55
mA
Oscillator Section
Initial accuracy
TA = 25
°
C,
VDD = 12 V to 18 V
TMIN to TMAX,
RT/CT Pin peak-to-peak
TA = 25
°
C,
RT/CT = 2 V,
See Note 3
50.5
53
55
kHz
Voltage stability
0.2%
1.0%
Temperature stability
See Note 2
1%
2.5%
Amplitude
1.9
V
Discharge current
RT/CT = 2 V,
See Note 4
7.7
8.4
9.0
mA
See Note 4
7.2
8.4
9.5
mA
Error Amplifier Section
Feedback input voltage, initial accuracy
VCOMP = 2.5 V,
VCOMP = 2.5 V,
VFB = 5.0 V
VOUT = 2 V to 4 V
See Note 2
TA = 25
°
C
2.475
2.500
2.525
V
Feedback input voltage, total variation
2.45
2.50
2.55
V
μ
A
dB
Input bias current
–0.1
–2.0
Open-loop voltage gain (AVOL)
Unity gain bandwidth
65
90
1.0
1.5
MHz
Power supply rejection ratio (PSRR)
VDD = 12 V to 18 V
VFB = 2.7 V,
VFB = 2.3 V,
VFB = 2.7 V,
VFB = 2.7 V,
60
dB
Output sink current
VCOMP = 1.1 V
VCOMP = 5V
RLOAD = 15 k to GND
RLOAD = 15 k to VREF
2
14
mA
Output source current
–0.5
–1.0
mA
High-level output voltage (VOH)
5
6.8
V
Low-level output voltage (VOL)
0.1
1.1
V
Current Sense Section
Gain
See Note 5, 6
2.85
3.00
3.15
V/V
Maximum input signal
VFB < 2.4 V
VDD = 12 V to 18 V, See Note 2, 5
0.9
1.0
1.1
V
Power supply rejection ratio (PSRR)
70
dB
μ
A
ns
Input bias current
–0.1
–2.0
CS to output delay
35
70
COMP to CS offset
NOTE: 1. Adjust VDD above the start threshold before setting at 15 V.
NOTE: 2. Ensured by design. Not production tested.
NOTE: 3. Output frequencies of the UCC38C41, UCC38C44 and the UCC38C45 are half the oscillator frequency.
NOTE: 4. Oscillator discharge current is measured with RT = 10 k
to VREF.
NOTE: 5. Parameter measured at trip point of latch with VFB = 0 V.
VCOM
VCS
VCS = 0 V
1.15
V
NOTE: 6. Gain is defined as ACS
,0V
VCS
900mV
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