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參數(shù)資料
| 型號： | UCC3941-5D |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 179K |
| 代理商： | UCC3941-5D |
6
UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
Programming the Power Limit
The UCC3941 incorporates an adaptive power limit con-
trol which modifies the converter current limit as a func-
tion of input voltage. In order to program the function, the
user simply determines the output power requirements
and makes an initial converter efficiency estimate. The
programming resistor is chosen by:
R
n
Pn V
PL
OUT
BAT
=
11 8
026
67
.
–.
Where
n is the initial efficiency estimate. For 500mW of
output power, with a 1.0V input, and an efficiency esti-
mate of 0.75:
()
()( )
RPL ==
11 8 0 75
05
0 26 0 75 1 0
67
22
..
.– .
.
–.
For decreasing values of RPL, the power limit increases.
Therefore, to insure that the converter can supply
500mW of output power, a power limiting resistor of less
than 22
must be chosen.
()
PV
I
L
BAT
L
=
11.8
2+ 6.7
+1.0 0 . 26
0.67W
2
This power limiting setting will support 0.5W of output
power. It should be noted that the power limit equation
contains an approximation which results in slightly less
actual input power than the equation predicts. This dis-
crepancy results from the fact that the average current
delivered to the load will be less than the peak current
set by the power limit function due to current ripple. How-
ever, if the ripple component of the current is kept low,
the power limit equation can be used as an adequate es-
timate of input power. Furthermore, since an initial effi-
ciency estimate was required, sufficient margin can be
built into this estimate to insure proper converter opera-
tion. The 6.2
external power limit resister in Fig. 3-5 will
result in approximately 700mW of power capability with a
APPLICATION INFORMATION (cont.)
5
8
1
7
6
VOUT
SW
10SN100M
100
F
R
PL
6.2
WCR0805-6R207
4
3.3V AT 500mW
2
SD
VGD
10
F
OPEN =
SD
3
VIN
10
F
MMSZ5240BT1
+1V TO 3.5V
DT3316P-223
22
H
PLIM
SGND
PGND
UCC3941-3
8V
Figure 3. Dual output synchronous boost 3.3V
version.
UDG-98163
5
8
1
7
6
VOUT
SW
10SN100M
100
F
R
PL
6.2
WCR0805-6R207
4
5.0V AT 500mW
2
SD
VGD
10
F
OPEN =
SD
3
VIN
10
F
MMSZ5240BT1
+1V TO 5.5V
DT3316P-223
22
H
PLIM
ADJ
PGND
UCC3941-5
8V
Figure 4. Dual output synchronous boost 5V version.
UDG-98159
5
8
1
7
6
VOUT
SW
10SN100M
100
F
R
PL
6.2
WCR0805-6R207
4
3.3V AT 500mW
2
SD
VGD
10
F
OPEN =
SD
3
VIN
10
F
MMSZ5240BT1
+1V TO VOUT + 0.5V
DT3316P-223
22
H
PLIM
SGND
PGND
UCC3941-3
10V
R1
R2
VOUT=1.25(1+
)
R1
R2
Figure 5. Dual output synchronous boost ADJ
version.
UDG-98164
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參數(shù)描述 |
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