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參數資料
| 型號： | UDA1350ATS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | IEC 958 audio DAC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁數： | 14/32頁 |
| 文件大?。?/td> | 124K |
| 代理商： | UDA1350ATS |
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2000 Mar 29
14
Philips Semiconductors
Preliminary specification
IEC 958 audio DAC
UDA1350ATS
8.6.4
D
ATA WRITE MODE
The data write mode is explained in the signal diagram of
Fig.5. For writing data to a device, four bytes must be sent
(see Table 6):
1.
One byte starting with ‘01’ for signalling the write
action to the device, followed by the device address
(‘011000’ for the UDA1350ATS).
2.
One byte starting with a ‘0’ for signalling the write
action, followed by 7 bits indicating the destination
address in binary format with A6 being the MSB and
A0 being the LSB.
3.
Two data bytes with D15 being the MSB and D0 being
the LSB.
Itshouldbenotedthateachtimeanewdestinationregister
address needs to be written, the device address must be
sent again.
8.6.5
D
ATA READ MODE
For reading data from the device, first a prepare read must
be done and then data read. The data read mode is
explained in the signal diagram of Fig.6.
For reading data from a device, the following six bytes are
involved (see Table 7):
1.
One byte with the device address including ‘01’ for
signalling the write action to the device.
2.
One byte is sent with the register address from which
dataneedsto beread.Thisbytestartswitha ‘1’,which
indicates that there will be a read action from the
register, followed again by 7 bits for the destination
address in binary format with A6 being the MSB and
A0 being the LSB.
3.
One byte with the device address including ‘11’ is sent
to the device. The ‘11’ indicates that the device must
write data to the microcontroller.
4.
One byte, sent by the device to the bus, with the
(requested) register address and a flag bit indicating
whether the requested register was valid (bit is logic 0)
or invalid (bit is logic 1).
5.
Two bytes, sent by the device to the bus, with the data
information in binary format with D15 being the MSB
and D0 being the LSB.
Table 6
L3 write data
Table 7
L3 read data
BYTE
L3 MODE
ACTION
FIRST IN TIME
LATEST IN TIME
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
1
2
3
4
address
data transfer
data transfer
data transfer
device address
register address
data byte 1
data byte 2
0
0
1
0
1
1
0
0
0
A6
D14
D6
A5
D13
D5
A4
D12
D4
A3
D11
D3
A2
D10
D2
A1
D9
D1
A0
D8
D0
D15
D7
BYTE
L3 MODE
ACTION
FIRST IN TIME
LATEST IN TIME
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
1
2
3
4
5
6
address
data transfer
address
data transfer
data transfer
data transfer
device address
register address
device address
register address
data byte 1
data byte 2
0
1
1
1
0
1
1
0
0
0
A6
1
A6
D14
D6
A5
0
A5
D13
D5
A4
1
A4
D12
D4
A3
1
A3
D11
D3
A2
0
A2
D10
D2
A1
0
A1
D9
D1
A0
0
A0
D8
D0
0 or 1
D15
D7
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